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EE 613 VLSI Design

EE 613 VLSI Design. Advisor: Jin-Fu Li TA: Shin-Yo Lin. Schedule. Requirement. You can assign project by yourself (Gate counts at least 5K). The two persons enjoy project. Submit to sub-module reports per week. Oral Presentation

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EE 613 VLSI Design

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  1. National Central University EE 613 VLSI Design EE 613VLSI Design Advisor: Jin-Fu Li TA: Shin-Yo Lin

  2. National Central University EE 613 VLSI Design Schedule

  3. National Central University EE 613 VLSI Design Requirement • You can assign project by yourself (Gate counts at least 5K). • The two persons enjoy project. • Submit to sub-module reports per week. • Oral Presentation • Briefly explain your sub-module reports and progress by a week. • Simulation, Waveform, Layout.

  4. Circuit Design HSPICE Simulation &Comparison ChipSpecification Verilog Layout Simulation &Comparison PDRACULA Verification GDSII File National Central University EE 613 VLSI Design Design Flow

  5. 4 to 16 Instruction Decoder 8-bit Register A 8-bit Register B 8-bit Some MUX ALU & control logic 8-bit Register C 64 byte SRAM National Central University EE 613 VLSI Design CPU Block Diagram

  6. National Central University EE 613 VLSI Design Instruction Sets

  7. National Central University EE 613 VLSI Design ChipImplementation • CIC 0.35m education chip available areas are 1500m×1500m, take off area of 28 PAD remain 748m×748m.

  8. National Central University EE 613 VLSI Design Proposal Format 14 pt 12 pt NO MORE THAN TWO PAPERS!!

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