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Introduction to Computer Buses and Memory Systems in MARIE Architecture

Delve into MARIE's architecture exploring bus types, memory components, address structure, datapath, control units, and instruction sets. Learn about memory interleaving, microoperations, and program execution.

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Introduction to Computer Buses and Memory Systems in MARIE Architecture

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  1. Chapter 4 MARIE: An Introduction to a Simple Computer Linda Null, Julia Lobur

  2. Figure 04.UN01: "When you wish to produce a result by means of an instrument, do not allow yourself to complicate it." Leonardo da Vinci

  3. Figure 04.F01: a) Point-to-Point Buses b) Multipoint Buses -

  4. Figure 04.F02: The Components of a Typical Bus -

  5. Figure 04.F03: Backplane Bus -

  6. Figure 04.F04: a) N 8-Bit Memory Locations b) M 16-Bit Memory Locations -

  7. Table 04.T01: Calculating the Address Bits Required -

  8. Figure 04.F05: Memory as a Collection of RAM Chips -

  9. Figure 04.F06A: High-Order Memory Interleaving -

  10. Figure 04.F06B: Address Structure -

  11. Figure 04.F06C: First Two Modules -

  12. Figure 04.F07A: Low-Order Memory Interleaving -

  13. Figure 04.F07B: Address Structure -

  14. Figure 04.F07C: First Two Modules -

  15. Figure 04.F08: MARIE's Architecture -

  16. Figure 04.F09: Datapath in MARIE -

  17. Figure 04.F10: MARIE's Instruction Format -

  18. Table 04.T02: MARIE's Instruction Set -

  19. Figure 04.F11: The Fetch-Decode-Execute Cycle -

  20. Figure 04.F12: Fetch-Decode-Execute Cycle with Interrupt Checking -

  21. Figure 04.F13: Processing an Interrupt -

  22. Table 04.T03: A Program to Add Two Numbers -

  23. Figure 04.F14: A Trace of the Program to Add Two Numbers -

  24. Table 04.T04: An Example Using Labels -

  25. Table 04.T05: An Example Using Directives for Constants -

  26. Table 04.T06: MARIE's Extended Instruction Set -

  27. Table 04.T07: MARIE's Full Instruction Set -

  28. Figure 04.F15: Connection of MARIE's MBR to the Datapath -

  29. Table 04.T08: ALU Control Signals and Response -

  30. Figure 04.F16: Timing Diagram for the Microoperations of MARIE's Add Instruction -

  31. Figure 04.F17: Hardwired Control Unit -

  32. Figure 04.F18: Partial Instruction Decoder for MARIE's Instruction Set -

  33. Figure 04.F19: Ring Counter Using D Flip-Flops -

  34. Figure 04.F20: Combinational Logic for Signal Controls of MARIE's Add Instruction -

  35. Figure 04.F21: Microprogrammed Control Unit -

  36. Figure 04.F22: MARIE's Microinstruction Format -

  37. Table 04.T09: Microoperation Codes and Corresponding MARIE RTL -

  38. Figure 04.F23: Selected Statements in MARIE's Microprogram -

  39. Figure 04.F24: EAX Register, Broken into Parts -

  40. Table 04.T10: MIPS32 Register Naming Convention -

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