Esterel

1. Esterel By: Geoff Houston Britney Mendez Jon Calhoun Travis Blanchette

2. Content • Compliers • Alternative • New • Summary • Conclusion • References • Intro • Reactive systems • Features of reactive systems • The Language • Syntax • examples • FSM pro/con • compiling diagrams

3. Introduction • Situation 1 - stop light • Situation 2 - airplane flight computer • Situation 3 - vending machine • Situation 4 – anti-lock breaks

4. Reactive Systems • What are reactive systems • Why we need them • safety • efficient • quality control • Solutions to the situations

5. Features of Reactive systems • Deterministic • Formally Verifiable

6. Timeline • 1983 Developed by Gérard Berry • 1984 First semantics, LISP-based V2 compiler • 1988 Better semantics, Efficient V3 compiler • 1990 First hardware synthesis to FPGAs (DEC) • 1992 BDD-based verification facilities (Dassault) • 1995 Causality and cyclic circuits • 1997 Sequential optimization • 1999 V7 specification started • 2001 Esterel Technologies founded • 2003 Esterel V7 compiler released • 2005 First silicon produced by Esterel V7 • 2007 Fast code generation, System C backend • 2008 IEEE Standardization process started

7. Esterel – the language • Procedure Declarations • ProcedureDecls : • procedure ProcedureDeclList ; • Signal Declarations • Variable Declarations • Task Declarations • Sensor Declarations • Input Relation Declarations • Expressions • Statements • BNF Definition: • Module : • module ModuleIdentifier : • InterfaceDeclListopt • Statement • end moduleopt • Interface Declaration • Type Declarations • Constant Declarations • Function Declarations • FunctionDecls : • function FunctionDeclList;

8. Some definitions • Reactions • Instants or ticks • Status of a signal • Trace • Occurrences

9. Strong synchrony model • Also called Strong synchrony hypothesis • Import: Central to the theory of reactive systems

10. Some Syntax • var x := 0 : integer iniend; • Type identifier is either integer or boolean • Execution • In Parallel with the || operator • Sequentially with the ; operator • Modules are interfaces and instructions. • Modules are executed in parallel in an Esterel program.

11. Signals • A channel on which events occur • Two kinds: • Pure – present or absent in an instant, not both • Valued – pure signals with an associated value which only changes on event boundaries

12. Await/Emit • Await – waits for its occurrence to elapse, then terminates • await s • Emit – triggers an event on a signal s in the current instant and terminates instantly • emit s • emit s (e)

13. Module example module simple: input A, B, C; output D, E, F; loop await A; emit D; await A end || every B do emit F end || await B; emit E; await C; emit E; .

14. Input/output of module simple

15. Halt/Preemption and exceptions • Halt – fundamental time consumer in Esterel • Preemption do i1 watching o timeout i2 end • Exception trap E in i1 handle E do i2 end

16. Conditionals if e then i1 else i2 end present s then i1 else i2 end

17. Loops • Basic loop i end • do….upto • loop….each • every…do

18. trapHeartAttack in || runCheckHeart exitHeartAttack handle HeartAttackdo runRushToHospital end trap everyMorning do end every abort when 2 Lap abort everyStep do runJump|| runBreathe end every when15 Second; runFullSpeed loop eachLap abortrunSlowlywhen100 Meter; Signal Error Signal Process

19. The Stopwatch – Inputs/Outputs Lap/Reset Start/Stop Time Image Source:http://www.ewashtenaw.org/government/departments/cmhpsm/provider_information/images/Stopwatch%20for%20PI

20. The Stopwatch - Code module STOPWATCH: input SS, LR, SECOND; output TIME(integer); signal RESET, LAP, RUN, FROZEN in

21. The Stopwatch – Start/Stop Code loop await SS; do sustain RUN up to SS end ||

22. The Stopwatch – Lap/Reset Code every LR do present RUN then emit LAP else present FROZEN else emit RESET end end end ||

23. The Stopwatch – Frozen Display Code loop await LAP; trap T in sustain FROZEN || await LAP; exit T end end ||

24. The Stopwatch – Counter Code loop var second := 0 : integer in emit TIME(second) ; every SECOND do present RUN then second := second + 1 end ; present FROZEN else emit TIME(second) end end end upto RESET end .

25. Esterel as an FSM - Pros • Faster runtime • If FSM can be found, the program is guaranteed to run.

26. Esterel as an FSM - Cons • Exponential file size • Long compilation times • Debugging is challenging Exponential Growth of States

27. Esterel Compilation Alternatives • Intermediate code is generated instead of an FSM • Each instant is broken into a series of steps

28. Another example RESET module simple: input A, C; output B, E; every reset do loop await A; emit B; await A; emit E end || loop if B emit E; await C; emit A end end A B E B C A A E

29. A Typical Compiler C Void foo() { switch (st) { 0: if (IN=3) st = 5; goto L5; 1: if (RES) st = 3; goto L8; } L5: switch } Step 4: Generate C Esterel every RESET do loop await A; emit B; if C emit D; pause end || loop if B emit C; pause end end Step 1: Translate Step 2: Schedule Step 3: Sequentialize Concurrent Control-Flow Graph Scheduled CCFG Sequential Control-Flow Graph Stephen A.Edwards

30. Step 1: Build Concurrent CFG every RESET do loop await A; emit B; if C emit D; pause end || loop if B emit C; pause end end Reset 1 Fork 2 S A B B C C D S=2 S=1 Join

31. Step 2: Schedule Add arcs for communication RESET 1 s 2 A B B C C D S=1 S=2

32. RESET 1 s 2 A B B C C D s=2 s=1 Step 3: Concurrency removed RESET RESET RESET 1 S 2 1 1 s S A 2 2 B A T=0 T=1 B B B B B C 1 s 2 C C C 0 1 C T A D D C D s=2 s=1 s=1 S=2 S=1 s=1 S=2

33. Step 3: Sequentialize • Hardest part: Removing concurrency • Simulate the Concurrent CFG • Main Loop: • For each node in scheduled order, • Insert context switch if from different thread

34. Esterel Compiler Alternatives • Smaller filesize and compilation times • 20 min and 3.7mb vs 7s and 80kb • Causality checking is left to runtime present A else emit A end

35. Esterel Compiler Alternatives • Introduces several new elements within processes • Program counters • Set Calculator • Process status • Terminated (0) • Halted (1) • Waiting (-1)

36. Known Compilers • 1988: INRIA compiler (G. Berry) • 1999: SynopsysEsterel v5 Compiler (S. Edwards) • 1998: GMDEsterel compiler (A. Poigné, L. Holenderski) • 2001: Xerox TCCP time constraint language (V. Saraswat) • 2001: France TelecomEsterel->C compiler (Weil & Closse) • 2001: Cadence Esterel/C Language = ECL (Lavagno, Sentovich) • 2002: ColumbiaEsterel v5 Compiler (S. Edwards) • 2002: Kaiserslautern Quartz compiler / verifier (K. Schneider) • 2004: INRIAEsterel->FastC compiler (D. Potop) • 2005: DassaultSystèmesEsterel for PLCs compiler • 2006: KaiserslauternAverest system (K. Schneider)

37. Summary • Features – reactive template, concurrency, signals, • Benefits – C files, Concurrency for control systems, deterministic, finite state lang, implemented in hardware • Suckage - bad for data flow, C files huge, C files inefficient and bulky, Semantic challenges: loop emit E end impossible

38. Conclusion • Proposal for Esterel v7 to make it more efficient without the hardware. • Great with the right hardware. • started SCADE

39. References • Prof. Stephen A. Edwards Columbia University, New York www.cs.columbia.edu/~sedwards • The Esterel v5 Language Primer Version 5.21 release 2.0 G´erard Berry Centre de Math´ematiquesAppliqu´eesEcole des Mines and INRIA http://dvlabweb.soe.ucsc.edu/ucsc/esterel/esterel_primer.pdf • An Esterel Compiler for a Synchronus / Reactive Development System by Stephan Edwards

40. Esterel By: Geoff Houston Britney Mendez Jon Calhoun Travis Blanchette