Synchronous Languages and System Design with Esterel

1. Synchronous Languagesand System Design with Esterel Ellen Sentovich Cadence Berkeley Laboratories

2. Outline • Context : Reactive Systems • Principles : Synchronous languages • Esterel in-depth • Language, Compilation • Causality • Optimization and Verification • New applications: ECL • Implementing Esterel on CFSM networks

3. System Design • Systems produce a steady sequence of input/output sequences • Inconvenient to specify sequences; need models and languages • Model • Simple and intuitive • Accurate enough model of physical reality • Mathematically efficient • General enough to allow different implementation styles • Language • Accurate expression of the model • Convenient and efficient expression of the design • Analysis • Implementation • compilation to hardware, software

4. Lustre SCADE Signal Esterel Statecharts Argos EsterelStudio Reactive Systems signals signals control data sensors values

5. Applications • Software and hardware controllers • process control, embedded systems,data-path control • Communication Protocols • software protocols,bus interfaces,cache coherence • Drivers • man-machine interface,systems drivers,pipeline logic Concurrency + Determinism

6. Reactive System Characteristics • Reactivity • continually react at a speed determined by the environment • Concurrency • at least between system and environment • Strict time and reliability requirements • Deterministic • Mixed hardware/software implementations

7. Synchronous Systems Cycle based read inputs compute reaction produce outputs Synchronous within the same cycle at the same time (0-delay) (must be checked on implementation) Synchronous control propagation signal broadcasting Equivalent FSM implementation (good analysis techniques)

8. Synchronous Languages • Invented for the design of reactive kernels • not the interactive interface or data management • Programmer views system as an instantaneous reactor to events • Program behavior is completely deterministic • Attempt to resolve concurrency and non-determinism (in other models)

9. Esterel: Background • Esterel is one of a set of synchronous languages developed in France: • Esterel: reactive control • Lustre, Signal: data flow • Argos, SyncCharts: graphical • Esterel development goal: natural expression of control • Specific statements to deal with time, preemption • Departure from concurrency as interleaving and rendez-vous to concurrency as instantaneous propagation of control

10. Esterel: Background • Synchronous programming environment... • Language: • For control-dominated, reactive systems • Constructs for sequencing, concurrency, preemption • Compiler: • Produces sorted Boolean equations • Causality checking, symbolic debugging, verification • Implementation as C-code or digital circuits

11. Esterel: Basic Principles • Synchronous hypothesis : instantaneouscommunication • Communication via broadcast signals (event) • signals, sensors, variables • pure, valued • Boolean and arithmetic operators • Modularity : program = collection of modules • Concise programs : write things once !! • Concurrency, sequencing, preemption • Well-defined semantics

12. Overview of Syntax • Signal reading/writing emit S emit S(value) present S then p else q • Basic control and looping: halt loop p end run module • Sequencing, concurrency p ; q p || q • Preemption suspend p when S abort p when S weak abort when S abort when immediate S

13. Syntax : await statement • Most basic signal control statement await S • Equivalent to abort loop halt end when S • Note: “Await” always stops • consider await S; await S • versus await immediate S; await immediate S

14. Variables and Ordering • Variable manipulation (local) V := value if V=value then p else q • Variable computations : ordered V := 5; V := V+1; Y := V; emit S(V) • Signal emissions (communication) : unordered Legal: emit S; emit S Illegal:emit S(3); emit S(5)(non-deterministic) • Signal computations : ordered Well-defined: emit S; present S Undefined: present S then emit S

15. The ABRO Example R R A B R AB/O B/0 A/O • “Wait until both A and B have occurred, then output O, unless the reset R occurs” Number of states is exponential in inputs

16. The ABRO Example in Esterel • Wait until both A and Bconcurrency • Unless R preemption loop abort [await A || await B] ; emit O when R end Write things ONCE !! Code size is linear in inputs; efficient circuit

17. Compilation • Esterel program  extended finite state machine • finite # inputs, deterministic reaction finite program • FSM + data computations • Can be compiled to a single automata - EXPENSIVE!! • exhaustive exploration of set of control states • Esterel v3 • Can be translated to sorted Boolean equations • Esterel v5 • State machine is represented implicitly

18. Translation to Boolean Circuits • Structural translation • Network of interconnected cells • Implementation of control: • control signal runs through the circuit • boot signal : latch, initially 1, thereafter 0 • Each cell contains • signal input/output; control input/output • suspend, kill, resume signals • return codes (nested preemption) • One register per halting statement

19. Translation to Boolean Circuits control for q control S control for p control • present S then p else q

20. Causality • Cycles occur naturally in Esterel specifications • Cyclic dependency between variables • Some are harmful, some not • The Causality Problem is analyzing these cycles and deciding which to accept • It is related to analyzing hardware in circuits • Combinational cycles • How do we define a causally correct program? • We want a unique, comprehensible solution • All present signals must be emitted somewhere • A solution is a set of consistent assignments to all signals • Need to be able to express program in a non-cyclic way Constructive causality

21. Harmful Cycles No Boolean solution (non-reactive), or several solutions (non-deterministic) Electrically unstable Useless !

22. X X = X X X = not X present X then emit X end present X else emit X end

23. Harmless Cycles Unique Boolean solution Electrical stabilization in bounded time => behaves as if acyclic Natural in Esterel programming Natural in high-level hardware synthesis Possible exponential saving in space!

24. X I Y present I then present X then emit Y end else present Y then emit X end end

25. I X Y J X = I and not Y Y = J andnot X OK unless I = J = 1

26. Combinational Cycles in Sequential Circuits 1 X Y 0 The non-constructive state (1,1) is unreachable => reachability analysis needed

27. C C 1 0 F G 0 1 Y X 1 0 C Naturally occurring harmless cycles: Operator sharing (S. Malik) Y = if C then G(F(X)) else F(G(X))

28. Causality: A Real Example GrantOut TokenOut GrantOut TokenOut GrantOut T Cell n AckOut ReqIn TokenIn GrantIn ReqIn AckOut TokenOut GrantOut Cell 1 ReqIn AckOut TokenIn GrantIn GrantIn GrantIn TokenIn • Bus arbitration

29. Strange Cycles Unique Boolean solution But electrically unstable ! => Electricity = Boolean calculus /

30. X = X Y = X and not Y X X = 0 X = 1 ? Y Want to build a theory with stable solutions. Also cheaper for compiler (interpretation possible)

31. ToBe Hamlet: ToBe = ToBe or not ToBe present ToBe then emit ToBe else emit ToBe end

32. Constructive Causality in Esterel Step through program Analyze whatmust be done (emit) whatcannotbe done (no possible emit) what can be done Set a signalpresentiff itmustbe emitted Set a signalabsentiff itcannotbe emitted Constructive causality permits interpretation

33. Executing Constructive Causality • module P1: • input I; • output O; • signalS1, S2 in • present I then emit S1 end • || • present S1else emit S2end • || • present S2 then emit Oend • end signal • end module

34. Analogy: constructive circuits Circuits are Boolean proof builders 0 0 0 0 0 Trace values from inputs to outputs, never guessing a value Analysis equivalent to electron flow in a circuit A causal program is equivalent to an electrically stable circuit, acyclic circuit

35. Constructive Boolean Logic Derive facts from facts E=0 F=0 E=1 F=1 E and F = 0 E and F = 0 E and F = 1 E=0 E=1 not E = 1 not E = 0 X=E E=b X=b Cannot determine E or not E unless E is known!

36. X = I and not Y Y = J and not X (1) I=0 (2) J=1 (3) X=0 from (1) (4) not X=1 from (3) (5) Y=1 from (2) and (4) (1) I=1 (2) J=0 (3) Y=0 from (2) (4) not Y=1 from (3) (5) X=1 from (2) and (4) No proof of X and Y if I=J=1

37. Semantic model : Scott’s 3-valued logic B = { , 0, 1} View circuit as fixpoint equation X = F(X, I) X=b holds in fixpoint iff provable T T

38. Main Theorem (Shiple Berry fromBrzozowski - Seger) Given a circuit and an input : X=b provable in CBL (proving facts) <=> X=b in the fixpoint (Scott’s view) <=> X stabilizes to b for any delay assignment (circuit view) Compositionality

39. Algorithms (Esterel v5) Interpretation Input-dependent analysis linear time Compilation (Shiple = Malik + Bourdoncle) Input-independent fixpoint analysis: Combinational loops are broken three-valued simulation performed (BDDs) reachable state computation (BDDs) Check that all feedback wires are well-defined Expensive!Interpretation option in Esterel ==> equivalent acyclic version

40. I=0 . J=1 X : 2 Y : 2 J=1 . X=0 X : 1 Y : 2 X : 1 Y : 1 X=0 X : 1 Y : 0 X : 0 Y : 0 Y=1 Interpretation Example X = I and not Y Y = J and not X facts unknowns X : 1 Y : 0

41. I=1 . J=1 X : 2 Y : 2 J=1 X : 1 Y : 2 X : 1 Y : 1 X = I and not Y Y = J and not X Deadlock = proof search stops

42. Dual-Rail Encoding to Implement Constructive Analysis X set of inputs that set X to 1 X set of inputs that set X to 0 The circuit is constructive for all inputs such that X or X = 1 for all X { X X = I and Y X = I or Y Y = J and X Y = J or X X = I and not Y Y = J and not X 3-valued: 01 = 0, 10 = 1, 00 = unknown

43. { I = I I = not I for I input X = 0 X = 0 Y = 0 Y = 0 Fixpoint iteration X = I and Y X = I or Y Y = J and X Y = J or X X = I and J X = I Y = J and I Y = J X = 0 X = I Y = 0 Y = J Need XX = 0, YY = 0; X + X = 1, Y + Y = 1 ((I and J) or I) and ((J and I) or J)) not(I and J)

44. Causality Summary Constructive Boolean logic characterizes delay-independent digital circuits Solves the causality problem for Esterel Strong user request! Compositional semantics Good implementation and decision algorithms

45. Graphical Symbolic Debugging • Xes

46. Optimization • Standard logic synthesis techniques can be applied to generated hardware • Finite state machine optimization and analysis • Esterel state encoding: • locally group-hot • efficient implementation • far more latches than the minimum • Latch minimization algorithms • exploit the latch/logic tradeoff • progressively more powerful algorithms

47. Latch Optimization L 0 1 L1 … Ln-1 1 1 1 1 • Replacement of latches with logic • compute the reachable state set • compute sets of latches that can be replaced • single latch removal : Rl  Rl’= 0 • 2-for-1 removal : Rij  Ri’j’ + Ri’j  Rij’ = 0 Reachable states Karnaugh map

48. Latch Optimization In Out Circuit L D L’ E • Generate decoding logic • single-latch: remove latch • 2-for-1: remove two latches, add logic for one • Generate encoding logic • single-latch: E = Rl (dependent on other latches)

49. Latch Optimization : Exclusive Sets • Mutually exclusive latch activity await s1 || await s2 || await s3 ; await s4 || await s5 || await s6 • Latch corresponds to each wait • (s1, s2, s3) # (s4, s5, s6) • Replace 6 latches with 3 plus a multiplexing latch

50. Latch Optimization : Results • Esterel encoding maintains the structure of the initial program • single latch removal is always beneficial • More sophisticated algorithms exploit latch/logic tradeoff • Cost functions depend on circuit size, BDD size • Typically 2-for-1 is performed until logic becomes prohibitively expensive • Verification times are improved