ECE 407 Computer Aided Design for Electronic Systems Spring 2009 CMOS Logic Instructor: Maria K. Michael

1. ECE 407 Computer Aided Design for Electronic Systems Spring 2009 CMOS Logic Instructor: Maria K. Michael MKM -

2. Overview • MOS transistors (nMOS, pMOS) • CMOS processing technology • CMOS design/layout rules • MOS transistors as ideal switches • CMOS logic: • Inverter • Combinational logic • NAND/NOR gates • Compound/Complex gates • Multiplexers/XOR gates • Sequential logic cells (latches, FFs) MKM -

3. Gate Source Drain Substrate (bulk) Insulation Metal-Oxide-Semiconductor (MOS) transistors • Silicon, basic starting material • Created by superimposing several layers of conducting (αγωγός) material, insulating (μόνωση) and transistor forming material • Construction process is carried out on a single crystal of silicon (wafer) MKM -

4. Typical MOS structure layer • Diffusion (doping of silicon w/ impurities) • Polysilicon (=polycrystalline silicon) for interconnect and transistor Gate • Aluminum (metal) for interconnect • All of the above are separated by insulating material/layers (silicon dioxide= oxide) Gate (polysilicon) (diffused silicon) Source Drain (diffused silicon) Substrate (bulk) (diffused silicon) Insulation (oxide) MKM -

5. Si Si Si Si Si Si e Si Si P Si Si B Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Semiconductor Materials and Properties • Valence electrons: electrons in the outmost shell of an atom • A silicon atom has 4 valence electrons • A silicon crystal at ~0C is an insulator • To make transistors, it is necessary to make silicon act as a semiconductor strong bonds, no electron movement silicon atom w/ 4 valence electrons silicon crystal extra electron hole Add holes on silicon: add impurities (other material) w/ fewer # of valance electrons eg. Boron (B), w/ 3 v.e. Add (diffuse/dope) electrons on silicon: add impurities (other material) w/ higher # of valance electrons eg. Phosphorous (P), w/ 5 v.e. acceptor impurity p-dopped/p+ donor impurity n-dopped/n+ MKM -

6. CMOS transistors • CMOS = Complementary Metal Oxide Semiconductors • nMOS (n-type) • Negatively diffused silicon (rich in electrons) for Drain and Source, in positively diffused substrate • pMOS (p-type) • Positively diffused silicon (rich in holes) for Drain and Source, in negatively diffused substrate • Gate is Polysilicon MKM -

7. p-type diffusion n-type diffusion G G p+ n+ p+ n+ D D S S p+ n+ substrate substrate p-type substrate n-type substrate CMOS transistors Physical structure of pMOS(cross section) Physical structure of nMOS(cross section) • 3 terminals: G, S, D (substrate 4th) • G: control input, affects flow of electrons in the channel pMOS schematic nMOS schematic needs G=0 to conduct needs G=1 to conduct MKM -

8. CMOS transistors • A MOS transistor is a “majority carrier” (φορέας πλειοψηφίας) • Current between S and D (channel) is modulated by a voltage applied to G S n+ S p+ nMOS pMOS substrate substrate G G p+ n+ D D n+ p+ • majority carriers = electrons • +voltage on G enhances the # of electrons in the channel •  conductivity increases • majority carriers = holes • -voltage on G enhances the # of holes in the channel •  conductivity increases MKM -

9. Threshold Voltage (Vth) • Most important parameter that characterizes the switching behavior of a transistor • Vth: the voltage at which a MOS transistor begins to conduct (turn-on). • For nMOS VG > Vth • For pMOS VG < Vth • The switching (turn on/off) is defined by the mode of a MOS device: • IDS = D-to-S current • VGS= G-to-S voltage • VDS= D-to-S voltage • VGD = G-to-D voltage to turn-on (very simplistic explanation!) determine the operation of the device MKM -

10. CMOS Processing Technology(Basic concepts) • base = SILICON, if pure it behaves as an insulator; to alter its conductivity, we add impurities called dopands (add electrons/holes) • 2 categories of dopands: • Donors: supply free electrons (ex. Phosphorus, Arsenic) • Acceptors: add holes (ex. Boron) • Wafer Processing: • Wafer: a thin slice of crystal silicon (grown at 1500C); size usually varies from 75-230mm in diameter and 0.25-1.00mm in thickness • Process starts with a silicon crystal, sliced into wafers • Each wafer is polished (at least one of its faces) to a flat, scratch-free mirror finish (this side is used to implement the CMOS devices) MKM -

11. CMOS Processing Technology(Basic concepts) • Oxidation: • To manufacture CMOS devices, silicon dioxide (SiO2) must be produced very reliably • Achieved by heating silicon wafers in an oxidizing atmosphere such as oxygen or water vapor • Lithography: • The process of transferring a pattern to a layer on a chip by utilizing appropriate masks • At each step of the fabrication process, impurities are introduced on certain areas of the wafer. Masks are used to define these areas. MKM -

12. CMOS Design Rules (also, Layout Rules) • Provide a necessary communication between the circuit designer and the process designer during the fabrication process • Specify to the designer certain geometric characteristics /constraints on the layout (so that design topology & geometry is preserved) • 2 issues: • Geometric reproduction of features by the mask-making lithographical process • Interaction between different layers • lamda () = size of smallest feature on transistor (usually 2 defines the technology) • –based rules = all rules (if possible) given as multiples of (see example in tbl 2.7, pg. 61 of your textbook) MKM -

13. MOS transistors as ideal switches • … MKM -

14. CMOS logic • … MKM -