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The MGPA ECAL readout chip for CMS

The MGPA ECAL readout chip for CMS. Multi–Gain Pre-Amplifier - 0.25 m m CMOS chip for CMS ECAL. OUTLINE Introduction & background Design Measured Performance Conclusions. Mark Raymond , Geoff Hall, Imperial College London, UK.

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The MGPA ECAL readout chip for CMS

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  1. The MGPA ECAL readout chipfor CMS Multi–Gain Pre-Amplifier - 0.25 mm CMOS chip for CMS ECAL OUTLINE Introduction & background Design Measured Performance Conclusions Mark Raymond, Geoff Hall, Imperial College London, UK. Jamie Crooks, Marcus French, Rutherford Appleton Laboratory, UK. IEEE Nuclear Science Symposium, Rome 2004 M. Raymond, Imperial College London IEEE NSS, Rome 2004

  2. CMS Electromagnetic Calorimeter ECAL X-section PbWO4 crystals ECAL barrel end-cap Compact Muon Solenoid ~ 75,000 Lead Tungstate scintillating crystals 60,000 barrel, 15,000 end-cap Hostile radiation environment PbWO4 crystals 2.2 x 2.2 cm2 23 cm M. Raymond, Imperial College London IEEE NSS, Rome 2004

  3. Crystal Readout 2 different types Barrel - Avalanche Photodiode (APD) good for high transverse magnetic field not so radiation hard 2/crystal -> ~ 200 pF detector capacitance 60 pC full-scale signal End-cap - Vacuum Photo-Triode (VPT) better radiation hardness OK for lower transverse magnetic field in end-cap v. low capacitance but cabling adds ~ 50 pF 16 pC full-scale signal challenge for front end readout chip 2 different signal sizes and input capacitance prefer to have just one chip for both APDs VPT M. Raymond, Imperial College London IEEE NSS, Rome 2004

  4. Background CMS ECAL dynamic range requirement ~ 16 bits to cover range from noise to full-scale signal General approach use multiple gain ranges -> high resolution with only 12 bit ADC only transmit value for highest gain channel-in-range => have to take decision on front end every 25 ns (LHC bunch spacing) Earlier version of CMS ECAL architecture range decision taken in preamplifier (complex chip), followed by single channel commercial ADC New architecture proposed following major ECAL electronics review, early 2002 3 parallel gain channels (MGPA), multi-channel ADC, range decision taken by logic in ADC chip use 0.25 mm CMOS to achieve: system simplifications: single 2.5V supply for all on-detector chips, power savings well known radiation hardness short production turnaround, high yield, cost savings Short timescale for development design begun mid 2002, first submission early 2003, fortunately worked well final version (only minor design revisions) available Spring 2004 12 bit ADCs 12 12 bits LOGIC 6 2 bits range 1 MGPA APD/VPT Multi-channel ADC M. Raymond, Imperial College London IEEE NSS, Rome 2004

  5. MGPA Target Specifications Barrel/Endcap read out using APD/VPT different capacitance and photoelectric conversion factors 3 gain ranges (1:6:12) sufficient to deliver required physics performance 40 ns pulse shaping trade-off between pile-up and noise (25 ns LHC bunch spacing) linearity and pulse shape matching specs demanding Vpk-25 Vpk M. Raymond, Imperial College London IEEE NSS, Rome 2004

  6. MGPA Architecture input stage CF chosen for max. poss. gain depending on barrel/end-cap RF chosen for 40 ns decay avoids pile-up CFRF external components => 1 chip suits barrel & end-cap differential current O/P stages external termination 2RICI = 40 nsec. => low pass filtering on all noise sources within chip 3 gain channels 1:6:12 set by resistors (on-chip), for linearity, feeding common- gate stages I2C interface to program: output pedestal levels DAC for test pulse (ext. trig.) i I2C and offset generator RI CI i VCM RG1 RI i DAC RI CI VCM RG2 RI ext. trig. CCAL input stage charge amp. RI CI VCM RG3 I/P RI diff. O/P stages gain stages RF CF RFCF VCM M. Raymond, Imperial College London IEEE NSS, Rome 2004

  7. Noise Sources common-gate gain stage vRf input stage Rf diff. output stage source follower Cf iCG RG vFET CIN iRG input stage high Cf (low gain) to cope with large full-scale signals => corresponding low Rf for 40 ns time const. => Rf noise dominates over input FET gain stage contribution can’t avoid for low gain range (RG big) but this range only used for larger signals so signal/noise still acceptable M. Raymond, Imperial College London IEEE NSS, Rome 2004

  8. Chip Layout layout issues gain channels segregated as much as poss. with separate power pads -> try to avoid inter-channel coupling lots of multiple power pads die size ~ 4mm x 4mm packaged in 100 pin TQFP (14mm x 14mm) offset gen. I2C diff. O/P stage high gain stage diff. O/P stage mid gain stage 1st stage low gain stage diff. O/P stage M. Raymond, Imperial College London IEEE NSS, Rome 2004

  9. Test Bench automated, controlled by PC running LabVIEW 14-bit VME ADC need high precision to measure performance to 12-bit level MGPA socketed on test board allows chip to chip comparison without change of external components prog. attenuator pulse gen. prog. delay MGPA test board 14-bit VME ADC M. Raymond, Imperial College London IEEE NSS, Rome 2004

  10. linear range Measured Output Pulse Shapes differential O/P signals from all 3 gain ranges 0 – 60 pC, 40 steps (logarithmic spacing) no signs of distortion in lower gain ranges when higher ranges saturate => effective gain channel separation in layout gain ratios 1 : 5.6 : 11.0 (c.f. 1 : 6 : 12) mid gain range low gain range high gain range Volts time [nsec] M. Raymond, Imperial College London IEEE NSS, Rome 2004

  11. Nonlinearity MGPA Version 2 MGPA Version 1 Nonlinearity given by: pk.pulse height – fit (to pk.ht.) fullscale signal 10 chips measured for each MGPA version v. similar results V1 cf. V2 nonlinearity within (or close to) ± 0.1% specification high gain range high mid mid Nonlinearity [% fullscale] Nonlinearity [% fullscale] low low charge injected [pC] charge injected [pC] M. Raymond, Imperial College London IEEE NSS, Rome 2004

  12. PSMF = Vpk-25 Vpk Pulse Shape Matching Output pulses spanning full-scale range for all 3 gains (11 / range) Vpk high normalise all 33 pulse shapes to max pulse ht. and superimpose Vpk-25 mid Pulse Shape Matching = (PSMF – Average PSMF) Average PSMF low ± 1% spec. (Average PSMF = average over all pulse shapes for all 3 gain ranges) M. Raymond, Imperial College London IEEE NSS, Rome 2004

  13. Noise BARREL END-CAP high gain chan. mid gain chan. high gain chan. mid gain chan. ENC [rms electrons] 7240+5.8/pF 7870+4.9/pF 3040+4.5/pF 3270+4.5/pF added capacitance [pF] added capacitance [pF] weak dependence on input capacitance as expected within spec. for high and mid-gain ranges: barrel < 10000 e, end-cap < 3500 e low gain range: barrel: 27300 e ± 12% end-cap: 8200 e ± 11% completely dominated by gain stage noise but signals large => electronic noise not significant (< 0.2% contribution to overall energy res’n.) M. Raymond, Imperial College London IEEE NSS, Rome 2004

  14. Radiation Tests low mid high pre-rad 5 Mrads 10 keV X-rays (spectrum peak) , dosimetry accurate to ~ 10%, doserate ~ 1 Mrad/hour, no anneal ~ 3% reduction in gain after 5 Mrads (50 kGy, 2 x end-cap worst case) no measurable effect on other performance parameters (noise, linearity, PSM ….) M. Raymond, Imperial College London IEEE NSS, Rome 2004

  15. On-chip Test Pulse external edge trigger ext. 10pF Volts MGPA I/P I2C simple DAC allows programmable (I2C) amplitude charge injection -> range of signal sizes for each gain range external trigger required allows functional verification during chip screening and in-system nsec. M. Raymond, Imperial College London IEEE NSS, Rome 2004

  16. Conclusion MGPA development successful – architecture suits both barrel and end-cap detector regions Analogue performance good gain linearity pulse shape matching noise rad-hard as expected power consumption 600 mW Current status 1st barrel supermodule contructed at CERN (barrel segment, 1700 channels) performance as expected (excellent noise uniformity) wafer mass production complete – large nos. packaged chips already available within (or v. close to) spec. 5 channel VFE card M. Raymond, Imperial College London IEEE NSS, Rome 2004

  17. Transistor Level Schematic M. Raymond, Imperial College London IEEE NSS, Rome 2004

  18. Barrel Energy Resolution x 12 x 6 x1 M. Raymond, Imperial College London IEEE NSS, Rome 2004

  19. Pulse Shape Measurements O/P signals probed individually 0 – 60 pC, 40 steps saturation in mid and high gain ranges no clamping outside linear range low gain range mid gain range high gain range Volts time [nsec] M. Raymond, Imperial College London IEEE NSS, Rome 2004

  20. I2C Pedestal Adjust I2C=0 I2C=50 I2C=100 ADC I/P range Volts VCM nsec. High gain range, ~ fullscale signal. I2C pedestal adjust sets offset current to diff O/P stage (one for each gain range) I2C ~ 50 about right in this case M. Raymond, Imperial College London IEEE NSS, Rome 2004

  21. Linearity and Pulse Shape Matching important for simple reconstruction of “true” pulse shape from samples coming from different gain ranges target specifications non-linearity <  0.1 % fullscale (each gain range) pulse shape matching factor: Vpk-25/Vpk <  1 % within and across all 3 gain ranges high gain range 25 ns samples linearize low gain range 12-bit range Vpk Vpk-25 M. Raymond, Imperial College London IEEE NSS, Rome 2004

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