SiPM Noise Implications (revised)

1. SiPM Noise Implications(revised) Alfons Weber CCLRC/RAL

2. TRIP-t Parameters • 32 synchronous channels • Integration window • 50 nsec to many μsec • reset time 50 nsec • Buffer depth • 48 deep analogue pipeline • 24 readable

3. 5.17µs 5.17µs 5.17µs 3.53s 3.53s 58ns 58ns 58ns 58ns 58ns 58ns 58ns 58ns 58ns 581ns 581ns 581ns 581ns 581ns 581ns 581ns 581ns Spill Structure Spill Structure • ASIC will work for any number of batches • < 24 batches • separation > 100 nsec Bunch Structure Chip Time Structure integration reset

4. Basic Performance • TRIP-t • Integrate charge for 270 nsec • Reset integrator for 50 nsec • Repeat above for up to 24 cycles • Timestamp • Use discriminator signal of integrated charge • Threshold between 0.5-3 pe • Charge readout • Integrated charge can be read-out without threshold • SiPM noise implications • No dead-time during integration cycles • Noise over real signal • Fake timestamp

5. Examples • 3 MHz of noise above 0.5 PE • probability to have a noise hit (ADC)3 MHz * 270 nsec = 80% • 30 kHz of noise above 2.5 PE • Probability to have noise hit (TDC) 30 KHz * 270 nsec = 0.8% • Mitigating factor • Could reduce integration window to 100 nsec • SiPMs are probably not that noisy • Multi-PE fraction may/will depend on integration time