Farhan Mohamed Ali (W2-1) Jigar Vora (W2-2) Sonali Kapoor (W2-3) Avni Jhunjhunwala (W2-4)

1. Presentation 10 MAD MAC 525 Farhan Mohamed Ali (W2-1)Jigar Vora (W2-2)Sonali Kapoor (W2-3) Avni Jhunjhunwala (W2-4) W2 Design Manager: Zack Menegakis 12th April, 2006 Top-Level Layout Project Objective: Design a crucial part of a GPU called the Multiply Accumulate Unit (MAC) which will revolutionize graphics.

2. MAD MAC 525 Status: • Project chosen • Specifications defined • Architecture • Design • Behavioral Verilog • Testbenches • Verilog : Gate Level Design • Floor plan • Schematics and Analog Verifications • Layout of basic gates and small modules • Top level layouts, Extractions, LVS, Simulations -> To be done • Full Chip Layout (50% complete) and Simulation

3. Block Diagram Input Input 16 Input 16 16 5 RegArray A RegArray B RegArray C 10 10 5 10 5 Multiplier Exp Calc Align 1 5 22 14 35 Control Logic & Sign Dtrmin Leading 0 Anticipator Adder/Subtractor 36 4 Normalize 14 1 5 Round Reg Y 1 10 5 15 16 Output 1 Ovf Checker

4. Design Decisions • Optimized the multiplier by using a carry look-ahead adder instead of a regular ripple carry adder in the last stage. • Allowed us to remove one of the pipeline stages from the multiplier because the prop delay went down. • Maximum of 8 Flip Flops per Pulse Generator

5. Timing Diagram

6. Floorplan

7. Full Chip Layout Progress….

8. The Sad Story of Exponents

9. Exponents Schematic

11. New Exponents Layout

13. 8-bit Register

15. Round Layout

19. Thoughts • Setup Time issues with having back to back registers. Probably need to buffer in between?

20. Questions??