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Instructor: Dan Garcia inst.eecs.berkeley /~cs61c

CS 61C: Great Ideas in Computer Architecture (Machine Structures) Lecture 30: Single-Cycle CPU Datapath Control Part 2. Instructor: Dan Garcia http:// inst.eecs.berkeley.edu /~cs61c. 9 problems with big data!.

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Instructor: Dan Garcia inst.eecs.berkeley /~cs61c

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  1. CS 61C: Great Ideas in Computer Architecture (Machine Structures)Lecture 30: Single-Cycle CPUDatapath Control Part 2 Instructor: Dan Garcia http://inst.eecs.berkeley.edu/~cs61c

  2. 9 problems with big data! In a refreshing NY Times Op-Ed, Gary Marcus and Ernest Davis tell us that Big Data is useful, but often overhyped as the panacea. Great as a tool, but keep in perspective! (Image Credit: New York Times) www.nytimes.com/2014/04/07/opinion/eight-no-nine-problems-with-big-data.html

  3. Review: Processor Design 5 steps Step 1: Analyze instruction set to determinedatapath requirements • Meaning of each instruction is given by register transfers • Datapath must include storage element for ISA registers • Datapath must support each register transfer Step 2: Select set of datapath components & establish clock methodology Step 3: Assemble datapath components that meet the requirements Step 4: Analyze implementation of each instruction to determine setting of control points that realizes the register transfer Step 5: Assemble the control logic

  4. Processor Design: 5 steps Step 1: Analyze instruction set to determinedatapath requirements • Meaning of each instruction is given by register transfers • Datapath must include storage element for ISA registers • Datapath must support each register transfer Step 2: Select set of datapath components & establish clock methodology Step 3: Assemble datapath components that meet the requirements Step 4: Analyze implementation of each instruction to determine setting of control points that realizes the register transfer Step 5: Assemble the control logic

  5. ALU Register-Register Timing: One Complete Cycle (Add/Sub) Clk Old Value New Value PC Instruction Memory Access Time Rs, Rt, Rd, Op, Func Old Value New Value Delay through Control Logic ALUctr Old Value New Value RegWr Old Value New Value Register File Access Time busA, B Old Value New Value ALU Delay busW Old Value New Value ALUctr RegWr Rd Rs Rt 5 5 5 Register Write Occurs Here busA 32 Rw Ra Rb busW 32 RegFile busB 32 clk

  6. ALU Register-Register Timing: One Complete Cycle Clk Old Value New Value PC Instruction Memory Access Time Rs, Rt, Rd, Op, Func Old Value New Value Delay through Control Logic ALUctr Old Value New Value RegWr Old Value New Value Register File Access Time busA, B Old Value New Value ALU Delay busW Old Value New Value ALUctr RegWr Rd Rs Rt 5 5 5 Register Write Occurs Here busA 32 Rw Ra Rb busW 32 RegFile busB 32 clk

  7. R[rt] = R[rs] op ZeroExt[imm16] op rs rt 31 16 15 0 immediate 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 bits 16 bits ALU 3c: Logical Op (or) with Immediate 31 26 21 16 0 immediate 6 bits 5 bits 5 bits 16 bits RegDst Rd Rt Writing to Rtregister (not Rd)!! 1 0 RegWr Rs Rt ALUctr 5 5 5 busA 32 Rw Ra Rb 32 RegFile busB 32 What about Rt Read? 0 32 clk imm16 1 ZeroExt 16 32 ALUSrc

  8. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits ALU 3d: Load Operations • R[rt] = Mem[R[rs] + SignExt[imm16]]Example: lw rt,rs,imm16 RegDst Rd Rt 1 0 RegWr Rs Rt ALUctr 5 5 5 busA 32 Rw Ra Rb 32 RegFile busB 32 0 32 clk imm16 1 ZeroExt 16 32 ALUSrc

  9. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 1 0 ALU 0 1 3d: Load Operations • R[rt] = Mem[R[rs] + SignExt[imm16]] Example: lw rt,rs,imm16 MemtoReg ALUctr RegDst Rd Rt RegWr Rs Rt 5 5 5 busA 32 Rw Ra Rb busW 32 RegFile busB 32 0 32 clk Adr imm16 1 Extender Data Memory 16 32 clk ALUSrc ExtOp

  10. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 1 0 ALU 0 1 3e: Store Operations • Mem[ R[rs] + SignExt[imm16] ] = R[rt] Ex.: sw rt, rs, imm16 MemtoReg ALUctr RegDst Rd Rt MemWr RegWr Rs Rt 5 5 5 busA 32 Rw Ra Rb busW 32 RegFile busB 32 0 32 clk 32 WrEn Adr imm16 Data In 1 Extender Data Memory 16 32 clk ALUSrc ExtOp

  11. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 1 0 ALU 0 1 3e: Store Operations • Mem[ R[rs] + SignExt[imm16] ] = R[rt] Ex.: sw rt, rs, imm16 MemtoReg ALUctr RegDst Rd Rt MemWr RegWr Rs Rt 5 5 5 busA 32 Rw Ra Rb busW 32 RegFile busB 32 0 32 clk 32 WrEn Adr imm16 Data In 1 Extender Data Memory 16 32 clk ALUSrc ExtOp

  12. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 3f: The Branch Instruction beq rs, rt, imm16 • mem[PC] Fetch the instruction from memory • Equal = R[rs] == R[rt] Calculate branch condition • if (Equal) Calculate the next instruction’s address • PC = PC + 4 + ( SignExt(imm16) x 4 ) else • PC = PC + 4

  13. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 00 PC Datapath for Branch Operations beqrs, rt, imm16 Datapathgenerates condition (Equal) Inst Address Equal nPC_sel 4 ALUctr RegWr Rs Rt Adder 5 5 5 busA 32 Rw Ra Rb = busW 32 Mux RegFile ALU busB Adder 32 clk clk PC Ext Already have mux, adder, need special sign extender for PC, need equal compare (sub?) imm16

  14. 31 26 21 16 0 op rs rt immediate Inst Memory Adr MUX ctrl 00 PC Q: What logic gate? Instruction Fetch Unit including Branch • if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 ; else PC = PC + 4 Instruction<31:0> nPC_sel Equal • How to encode nPC_sel? • Direct MUX select? • Branch inst. / not branch inst. • Let’s pick 2nd option nPC_sel 4 Adder 0 Mux 1 Adder imm16 clk PC Ext

  15. Inst Memory Adr Adder Adder Mux 1 0 = 00 ALU 0 PC 0 WrEn Adr 1 1 Extender Data Memory PC Ext Putting it All Together:A Single Cycle Datapath Instruction<31:0> <0:15> <21:25> <16:20> <11:15> Rs Rt Rd Imm16 RegDst nPC_sel MemtoReg ALUctr Rd Rt Equal MemWr RegWr Rs Rt 4 5 5 5 busA 32 Rw Ra Rb busW 32 RegFile busB 32 32 clk 32 clk imm16 Data In 16 32 clk imm16 ExtOp ALUSrc

  16. 1 0 00 ALU PC 0 1 DatapathControl Signals • ExtOp: “zero”, “sign” • ALUsrc: 0 regB; 1 immed • ALUctr: “ADD”, “SUB”, “OR” • MemWr: 1  write memory • MemtoReg: 0  ALU; 1 Mem • RegDst: 0 “rt”; 1 “rd” • RegWr: 1  write register ALUctr MemtoReg RegDst Rd Rt Inst Address MemWr nPC_sel & Equal RegWr Rs Rt 4 5 5 5 Adder busA 32 Rw Ra Rb 0 busW 32 RegFile busB 32 0 Mux 32 clk 1 Adder 32 WrEn Adr clk imm16 Data In PC Ext 1 Extender Data Memory 16 32 clk ALUSrc ExtOp imm16

  17. Given Datapath: RTL  Control Instruction<31:0> Inst Memory <0:5> <21:25> <16:20> <11:15> <0:15> <26:31> Adr Op Fun Rt Rs Rd Imm16 Control RegWr ALUSrc nPC_sel RegDst ExtOp ALUctr MemWr MemtoReg DATA PATH

  18. add rd, rs, rt MEM[PC] Fetch the instruction from memory R[rd] = R[rs] + R[rt] The actual operation PC = PC + 4 Calculate the next instruction’s address 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits RTL: The Add Instruction

  19. 00 PC Instruction Fetch Unit at the Beginning of Add • Fetch the instruction from Instruction memory: Instruction = MEM[PC] • same for all instructions Inst Memory Instruction<31:0> nPC_sel Inst Address 4 Adder Mux Adder clk PC Ext imm16

  20. 31 26 21 16 11 6 0 op rs rt rd shamt funct 1 0 = ALU 0 0 WrEn Adr 1 1 Extender Data Memory Single Cycle Datapath during Add R[rd] = R[rs] + R[rt] Instruction<31:0> instr fetch unit nPC_sel=+4 RegDst=1 <0:15> <21:25> <16:20> <11:15> clk Rd Rt Rs Rt Rd Imm16 ALUctr=ADD zero RegWr=1 Rs Rt MemtoReg=0 5 5 5 MemWr=0 busA 32 Rw Ra Rb busW 32 RegFile busB 32 32 clk 32 imm16 Data In 16 32 clk ALUSrc=0 ExtOp=x

  21. 00 PC Instruction Fetch Unit at End of Add • PC = PC + 4 • Same for all instructions except: Branch and Jump Inst Memory nPC_sel=+4 Inst Address 4 Adder Mux Adder clk PC Ext imm16

  22. P&H Figure 4.17

  23. Summary of the Control Signals (1/2) instRegister Transfer add R[rd]  R[rs] + R[rt]; PC  PC + 4 ALUsrc=RegB, ALUctr=“ADD”, RegDst=rd, RegWr, nPC_sel=“+4” sub R[rd]  R[rs] – R[rt]; PC  PC + 4 ALUsrc=RegB, ALUctr=“SUB”, RegDst=rd, RegWr, nPC_sel=“+4” ori R[rt]  R[rs] + zero_ext(Imm16); PC  PC + 4 ALUsrc=Im, Extop=“Z”, ALUctr=“OR”, RegDst=rt,RegWr, nPC_sel=“+4” lw R[rt]  MEM[ R[rs] + sign_ext(Imm16)]; PC  PC + 4 ALUsrc=Im, Extop=“sn”, ALUctr=“ADD”, MemtoReg, RegDst=rt, RegWr, nPC_sel = “+4” sw MEM[ R[rs] + sign_ext(Imm16)]  R[rs]; PC  PC + 4 ALUsrc=Im, Extop=“sn”, ALUctr = “ADD”, MemWr, nPC_sel = “+4” beq if (R[rs] == R[rt]) then PC  PC + sign_ext(Imm16)] || 00 else PC  PC + 4 nPC_sel = “br”, ALUctr = “SUB”

  24. add sub ori lw sw beq jump RegDst 1 1 0 0 x x x ALUSrc 0 0 1 1 1 0 x MemtoReg 0 0 0 1 x x x RegWrite 1 1 1 1 0 0 0 MemWrite 0 0 0 0 1 0 0 nPCsel 0 0 0 0 0 1 ? Jump 0 0 0 0 0 0 1 ExtOp x x 0 1 1 x x Subtract ALUctr<2:0> Add Subtract Or Add Add x 31 26 21 16 11 6 0 R-type op rs rt rd shamt funct add, sub immediate I-type op rs rt ori, lw, sw, beq target address jump J-type op Summary of the Control Signals (2/2) See func 10 0000 10 0010 We Don’t Care :-) Appendix A op 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010

  25. Boolean Expressions for Controller RegDst = add + subALUSrc = ori + lw + swMemtoReg = lwRegWrite = add + sub + ori + lw MemWrite = swnPCsel = beqJump = jump ExtOp = lw + swALUctr[0] = sub + beq (assume ALUctr is 00 ADD, 01 SUB, 10 OR)ALUctr[1] = or Where: rtype = ~op5  ~op4  ~op3  ~op2  ~op1  ~op0, ori = ~op5  ~op4  op3  op2  ~op1  op0lw = op5  ~op4  ~op3  ~op2  op1  op0sw = op5  ~op4  op3  ~op2  op1  op0beq = ~op5  ~op4  ~op3  op2  ~op1  ~op0jump = ~op5  ~op4  ~op3  ~op2  op1  ~op0 add = rtype  func5 ~func4 ~func3 ~func2 ~func1 ~func0sub = rtype  func5 ~func4 ~func3 ~func2 func1 ~func0 How do we implement this in gates?

  26. Controller Implementation opcode func RegDst add ALUSrc sub MemtoReg ori RegWrite “OR” logic “AND” logic MemWrite lw nPCsel sw Jump beq ExtOp jump ALUctr[0] ALUctr[1]

  27. Peer Instruction • Weshould use the main ALUto compute PC=PC+4 in order to save some gates • The ALU is inactivefor memory reads (loads) or writes (stores). 12 a) FF b) FT c) TF d) TT e) Help!

  28. Clicker Survey for CS RetreatIf we add more faculty, what should we do for upper-division courses? • We should have more sections of the same courses, so lecture is smaller • We should have more semester-long courses • We should have more half-semester-long courses

  29. Summary: Single-cycle Processor • Five steps to design a processor: 1. Analyze instruction set datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic • Formulate Logic Equations • Design Circuits Processor Input Control Memory Datapath Output

  30. Bonus Slides • How to implement Jump

  31. 31 26 25 0 J-type jump op target address Single Cycle Datapath during Jump • New PC = { PC[31..28], target address, 00 } Instruction<31:0> Jump= Instruction Fetch Unit nPC_sel= Rd Rt <0:15> <0:25> <21:25> <16:20> <11:15> Clk RegDst = Mux 1 0 Rt Rs Rd Imm16 TA26 ALUctr = Rs Rt RegWr = MemtoReg = 5 5 5 busA Zero MemWr = Rw Ra Rb busW 32 32 x 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 Data In 32 Data Memory imm16 Extender 32 16 Clk ALUSrc = ExtOp =

  32. 31 26 25 0 jump J-type op target address Single Cycle Datapath during Jump • New PC = { PC[31..28], target address, 00 } Instruction<31:0> Jump=1 Instruction Fetch Unit nPC_sel=? Rd Rt <0:15> <0:25> <21:25> <16:20> <11:15> Clk RegDst = x Mux 1 0 Rt Rs Rd Imm16 TA26 ALUctr =x Rs Rt RegWr = 0 MemtoReg = x 5 5 5 busA Zero MemWr = 0 Rw Ra Rb busW 32 32 x 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 32 Mux 1 WrEn Adr 1 Data In 32 imm16 Extender Data Memory 32 16 Clk ALUSrc = x ExtOp = x

  33. 31 26 25 0 J-type jump Inst Memory Adr Adder Mux Adder op target address Instruction Fetch Unit at the End of Jump • New PC = { PC[31..28], target address, 00 } Jump Instruction<31:0> nPC_sel Zero nPC_MUX_sel How do we modify thisto account for jumps? 4 00 0 PC 1 Clk imm16

  34. 31 26 25 0 jump J-type Inst Memory Adr Adder Mux Mux Adder op target address Instruction Fetch Unit at the End of Jump • New PC = { PC[31..28], target address, 00 } Jump Instruction<31:0> nPC_sel Zero • Query • Can Zero still get asserted? • Does nPC_sel need to be 0? • If not, what? nPC_MUX_sel 26 00 4 00 1 TA PC 0 4 (MSBs) 0 Clk 1 imm16

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