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Part 4 - Exception Hazards – one last kicker 3/24/04

Part 4 - Exception Hazards – one last kicker 3/24/04. Similar problem as the conditional branch An exception is an involuntary branch from a non-branching instruction that caused the exception Example: add $1, $2, $1 # assume the add overflows

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Part 4 - Exception Hazards – one last kicker 3/24/04

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  1. Part 4 - Exception Hazards – one last kicker3/24/04 • Similar problem as the conditional branch • An exception is an involuntary branch from a non-branching instruction that caused the exception • Example:add $1, $2, $1 # assume the add overflows • We need to immediately branch to the exception handler at entry point address: 0x40000040 • Must flush the instructions following the “add” & start fetching from the new address in the exception handler. • Overflow is detected in the EX stage – this is where the “add” will be • Must kill the “add” instruction dead in its tracks and not allow it to complete - so it will not clobber $1 – a valuable diagnostic for the programmer. • Do not allow this instruction to write results in WB stage. • Contrast this to the conditional jump, in which the beq instruction (that caused the jump) was allowed to complete.

  2. Exception Hazards: Data Path Changes • Insert a nop in the IF stage • Must be done directly – no control signals in IF/ID register • Need new control line, IF.Flush, from main controller • Flush instruction in ID stage • Zero out control signals • Need new control line, ID.Flush, from main controllerORed with the stall signal from Hazard Detection Unit for beq • Flush instruction in EX stage – the add instruction itself • Zero out control signals • Need new control line, EX.Flush, from main controller • beq did not flush this stage • Add additional input to PC MUX providing 0x40000040 jump address to the exception handler. • Save PC+4 in EPC register – exception handler will have to subtract 4 to get the address of the offending instruction.

  3. Data Path with Exception Hazard Support Fig. 6.55 The selector for the PC MUX must now be 2 bits: a line indicating the exception and the compare output – Not mentioned in book?

  4. An Example Scenario • Given the main program:0x40 sub $11, $2, $40x44 and $12, $2, $50x48 or $13, $2, $60x4C add $1, $2, $1 # overflow happens here0x50 slt $15, $6, $70x54 lw $16, 50($7) • Assume the exception handler starts with:0x40000040 sw $25, 1000($0)0x40000044 sw $26, 1004($0) • See fig 6.56 for response of data path. • Overflow detected during EX phase • 0x40000040 forced into PC • Cycle 6 shows the add and following instructions are flushed First instruction of exception handler is fetchedaddress following add is saved in EPC: 0x4C+4 = 0x50

  5. Data Paths for Exception Scenario Fig 6.56

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