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Figure 10.1. A flip-flop with an enable input.

E. 0. Q. Q. D. R. 1. Clock. Q. Figure 10.1. A flip-flop with an enable input. module rege (R, Clock, Resetn, E, Q); input R, Clock, Resetn, E; output Q; reg Q; always @( posedge Clock or negedge Resetn) if (Resetn == 0) Q <= 0; else if (E) Q <= R; endmodule.

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Figure 10.1. A flip-flop with an enable input.

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  1. E 0 Q Q D R 1 Clock Q Figure 10.1. A flip-flop with an enable input.

  2. module rege (R, Clock, Resetn, E, Q); input R, Clock, Resetn, E; output Q; reg Q; always @(posedge Clock or negedge Resetn) if (Resetn == 0) Q <= 0; else if (E) Q <= R; endmodule Figure 10.2. Code for a D flip-flop with enable.

  3. module regne (R, Clock, Resetn, E, Q); parameter n = 8; input [n-1:0] R; input Clock, Resetn, E; output [n-1:0] Q; reg [n-1:0] Q; always @(posedge Clock or negedge Resetn) if (Resetn == 0) Q <= 0; else if (E) Q <= R; endmodule Figure 10.3. An n-bit register with an enable input.

  4. Figure 10.4. A shift register with parallel-load and enable control inputs.

  5. module shiftlne (R, L, E, w, Clock, Q); parameter n = 4; input [n-1:0] R; input L, E, w, Clock; output [n-1:0] Q; reg [n-1:0] Q; integer k; always @(posedge Clock) begin if (L) Q <= R; else if (E) begin Q[0] <= w; for (k = 1; k < n; k = k+1) Q[k] <= Q[k-1]; end end endmodule Figure 10.5. A right-to-left shift register with an enable input.

  6. Sel Data Data Figure 10.6. An SRAM cell.

  7. Data Data 1 0 Sel 0 Sel 1 Figure 10.7. A 2 x 2 array of SRAM cells.

  8. d d d Data inputs n – 1 n – 2 0 Write Sel 0 Sel 1 Sel a 2 0 decoder a 1 m Address -to-2 a m m – 1 Sel m 2 ” 1 Read q q q Data outputs n – 1 n – 2 0 Figure 10.8. A 2m x n SRAM block.

  9. B = 0 ; while A  0 do a = 1 if then 0 B = B + 1 ; end if; A Right-shift ; end while; Figure 10.9. Pseudo-code for the bit counter.

  10. Please see “portrait orientation” PowerPoint file for Chapter 10 Figure 10.10. ASM chart for the pseudo-code in Figure 10.9.

  11. Figure 10.11. Datapath for the ASM chart in Figure 10.10.

  12. Figure 10.12. ASM chart for the bit counter datapath circuit.

  13. Please see “portrait orientation” PowerPoint file for Chapter 10 Figure 10.13. Verilog code for the bit-counting circuit.

  14. Figure 10.14. Simulation results for the bit-counting circuit.

  15. Decimal Binary 13 1 1 0 1 Multiplicand 11 1 0 1 1 Multiplier ´ ´ 13 1101 13 1 1 0 1 0 0 0 0 143 1 1 0 1 1 0 001111 Product (a) Manual method P = 0 ; – i = 0 n 1 for to do b = 1 if then i P = P + A ; end if; A Left-shift ; end for; (b) Pseudo-code Figure 10.15. An algorithm for multiplication.

  16. Please see “portrait orientation” PowerPoint file for Chapter 10 Figure 10.16. ASM chart for the multiplier.

  17. Please see “portrait orientation” PowerPoint file for Chapter 10 Figure 10.17. Datapath circuit for the multiplier.

  18. Please see “portrait orientation” PowerPoint file for Chapter 10 Figure 10.18. ASM chart for the multiplier control circuit.

  19. Please see “portrait orientation” PowerPoint file for Chapter 10 Figure 10.19. Verilog code for the multiplier circuit.

  20. Figure 10.20. Simulation results for the multiplier circuit.

  21. 15 Q 00001111 9 140 A 1001 100 01100 B 9 1001 50 10 001 45 10 01 10000 5 1001 1110 1001 (a) An example using decimal numbers R 101 (b) Using binary numbers R = 0 ; i = 0 n – 1 for to do R  A Left-shift ;  if R B then q = 1 ; i – R = R B ; else q = 0 ; i end if; end for; (c) Pseudo-code Figure 10.21. An algorithm for division.

  22. Please see “portrait orientation” PowerPoint file for Chapter 10 Figure 10.22. ASM chart for the divider.

  23. Figure 10.23. Datapath circuit for the divider.

  24. Please see “portrait orientation” PowerPoint file for Chapter 10 Figure 10.24. ASM chart for the divider control circuit.

  25. B 1001 10001100 A rr Clock cycle R A/ Q 0 Load A, B 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 Shift left 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 , ¬ 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 Shift left Q 0 1 0 , 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 ¬ 2 Shift left Q 0 0 , 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 ¬ 3 Shift left Q 0 0 , ¬ 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 Shift left Q 0 4 0 , ¬ 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 Subtract Q 1 5 0 , ¬ 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 Subtract Q 1 0 , ¬ Subtract Q 1 7 0 0 1 1 0 0 0 1 1 1 0 0 0 1 0 0 0 0 , ¬ Subtract Q 1 8 0 0 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 Figure 10.25. An example of division using n = 8 clock cycles.

  26. Please see “portrait orientation” PowerPoint file for Chapter 10 Figure 10.26. ASM chart for the enhanced divider control circuit.

  27. Please see “portrait orientation” PowerPoint file for Chapter 10 Figure 10.27. Datapath circuit for the enhanced divider.

  28. Please see “portrait orientation” PowerPoint file for Chapter 10 Figure 10.28. Verilog code for the divider circuit.

  29. Figure 10.29. Simulation results for the divider circuit.

  30. Please see “portrait orientation” PowerPoint file for Chapter 10 Figure 10.30. An algorithm for finding the mean of k numbers.

  31. Please see “portrait orientation” PowerPoint file for Chapter 10 Figure 10.31. Datapath circuit for the mean operation.

  32. Please see “portrait orientation” PowerPoint file for Chapter 10 Figure 10.32. ASM chart for the mean operation control circuit.

  33. Figure 10.33. Schematic of the mean circuit with an SRAM block.

  34. Figure 10.34. Simulation results for the mean circuit using SRAM.

  35. – i = 0 k 2 for to do A = R ; i – j = i + 1 k 1 for to do B = R ; j B < A if then R = B ; i R = A ; j A = R ; i end if ; end for; end for; Figure 10.35. Pseudo-code for the sort operation.

  36. Please see “portrait orientation” PowerPoint file for Chapter 10 Figure 10.36. ASM chart for the sort operation.

  37. Figure 10.37. A part of the datapath circuit for the sort operation.

  38. Figure 10.38. A part of the datapath circuit for the sort operation.

  39. Please see “portrait orientation” PowerPoint file for Chapter 10 Figure 10.39. ASM chart for the control circuit.

  40. Please see “portrait orientation” PowerPoint file for Chapter 10 Figure 10.40. Verilog code for the sorting circuit.

  41. Please see “portrait orientation” PowerPoint file for Chapter 10 Figure 10.41. Simulation results for the sort operation.

  42. Figure 10.42. Using tri-state buffers in the datapath circuit.

  43. Data Q D Clock Q E Figure 10.43. Clock enable circuit.

  44. ff ff ff ff ff ff ff ff Clock ff ff ff ff ff ff ff ff Figure 10.44. An H tree clock distribution network.

  45. Figure 10.45. A flip-flop in an integrated circuit.

  46. Figure 10.46. Flip-flop timing in a chip.

  47. Data Data Q Q D D (asynchronous) (synchronous) Clock Q Q Figure 10.47. Asynchronous inputs.

  48. V DD R V DD S Data R Data R R (a) Single-pole single-throw switch V DD (b) Single-pole double-throw switch with a basic SR latch Figure 10.48. Switch debouncing circuit.

  49. Q = 0 ; R = A ; – ((R B) > 0) while do – R = R B ; Q = Q + 1 ; end while ; Figure P10.1. Pseudo-code for integer division.

  50. 5 V 4 8 R a 3 7 Clock 555 (output) R b Timer 2 6 C 1 1 5 m 0.01 F Figure P10.2. The 555 programmable timer chip.

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