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SR Flip-Flop

The SR Flip-Flop. . . . . S. R. . . Q. Q. . . . . . . . . . . S R Action0 0 Keep state0 1 Q = 01 0 Q = 11 1 Undefined. . Clocked SR Flip-Flop. . . . . S. R. . . Q. Q. . . . . . . . . . . . . CLK. . . . . . . . Clocked D Flip-Flop. . . . . . . Q. Q. . . . . . . . . . . . . CLK

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SR Flip-Flop

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    1. SR Flip-Flop The SR Flip-Flop How it works Where does it fit with others Master-Slave Flip-Flops Negative Edge Triggered Flip-Flops

    2. The SR Flip-Flop

    3. Clocked SR Flip-Flop

    4. Clocked D Flip-Flop

    5. JK Flip-Flop

    6. T Flip-Flop

    7. Master-Slave Flip-Flop

    8. Master-Slave Flip-Flop Happens only once per clock cycle Acts as a double check

    9. Negative Edge Triggered D Flip-Flop

    10. Negative Edge Triggered D Flip-Flop Same benefits as a Master-Slave More efficient

    11. Finite State Machines What they are Build One

    12. What it is A way of modelling using “states” States Transitions Actions

    13. Example From Book (Pg. 464)? Modulo-4 Synchronous Counter 00 to 11 and repeats Has one input to reset the counter and start over

    14. How Do We Build This? Facts Two Bites of storage One input Two output Start with two D Flip-Flops Four states so four ANDs Two outputs so two ORs Plug it all together and fill in the gaps

    15. The Build (Pg. 467)?

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