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SR Flip-Flop

SR Flip-Flop. The SR Flip-Flop How it works Where does it fit with others Master-Slave Flip-Flops Negative Edge Triggered Flip-Flops. The SR Flip-Flop. S. S R Action 0 0 Keep state 0 1 Q = 0 1 0 Q = 1 1 1 Undefined. Q. Q. R. Clocked SR Flip-Flop. S. Q. CLK.

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SR Flip-Flop

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  1. SR Flip-Flop • The SR Flip-Flop • How it works • Where does it fit with others • Master-Slave Flip-Flops • Negative Edge Triggered Flip-Flops

  2. The SR Flip-Flop S S R Action 0 0 Keep state 0 1 Q = 0 1 0 Q = 1 1 1 Undefined Q Q R

  3. Clocked SR Flip-Flop S Q CLK Q R

  4. Clocked D Flip-Flop D CLK Q Q

  5. JK Flip-Flop J Q CLK Q K

  6. T Flip-Flop T CLK Q Q

  7. Master-Slave Flip-Flop J Q CLK Q K

  8. Master-Slave Flip-Flop • Happens only once per clock cycle • Acts as a double check

  9. Negative Edge Triggered D Flip-Flop Q CLK Q D

  10. Negative Edge Triggered D Flip-Flop • Same benefits as a Master-Slave • More efficient

  11. Finite State Machines • What they are • Build One

  12. What it is • A way of modelling using “states” • States • Transitions • Actions

  13. Example From Book (Pg. 464)‏ • Modulo-4 Synchronous Counter • 00 to 11 and repeats • Has one input to reset the counter and start over • RS1S0T+1T+10 0 0 01 010 0 1 10 100 1 0 11 110 1 1 00 001 0 0 00 001 0 1 00 001 1 0 00 001 1 1 00 00

  14. How Do We Build This? • Facts • Two Bites of storage • One input • Two output • Start with two D Flip-Flops • Four states so four ANDs • Two outputs so two ORs • Plug it all together and fill in the gaps

  15. The Build (Pg. 467)‏ RESET D Q q1 CLK Q D Q q0 Q

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