BIST / Test-Decompressor Design using Combinational Test Spectrum

1. BIST / Test-Decompressor Design using Combinational Test Spectrum Nitin Yogi Vishwani D. Agrawal Auburn University, Dept. of Elec. & Comp. Eng. Auburn, AL 36849, U.S.A. 13th IEEE / VSI VLSI Design and Test Symposium Bangalore, India 13th VLSI Design and Test Symposium

2. Outline • Problem Definition • Proposed Design Method • Spectral Analysis • BIST Architecture • Results • Results without reseeding • Results with reseeding • Conclusion 13th VLSI Design and Test Symposium

3. Problem Definition • To design a Test Pattern Generator (TPG) for Built-In Self Test (BIST) of combinational circuits achieving the following goals: • Given a set of pre-generated test vectors, replicate their effects in hardware • Low area overhead • Low test application times 13th VLSI Design and Test Symposium

4. Proposed Design Methodology Pre-generated test vectors Spectral properties Step 2 Step 1 Preprocess test vectors BIST implementation Determine prominent spectral components by spectral analysis BIST TPG gate-level netlist 13th VLSI Design and Test Symposium

5. Walsh Functions and Hadamard Matrix • Walsh functions: a complete orthogonal set of basis functions that can represent any arbitrary bit-stream. • Walsh functions form the rows of a Hadamard matrix. w0 w1 w2 w3 Walsh functions (order 3) H(3)= w4 w5 w6 w7 Example of Hadamard matrix of order 3 time 13th VLSI Design and Test Symposium

6. Test Vectors and Bit-streams Circuit Under Test (CUT) Outputs Input J Input 5 Input 3 Input 1 Input 4 Input 2 A binary bit-stream to be spectrally analyzed Vector 1 → Vector 2 → Vector 3 → Vector 4 → Vector 5 → Time Vector K→ 13th VLSI Design and Test Symposium

7. Spectrum: Input 1 of circuit s5378 Spectrum of ATPG bit-stream applied to input 1 of circuit s5378 Theoretical random noiselevel (16) 13th VLSI Design and Test Symposium

8. Spectrum: Input 9 of circuit s5378 Spectrum of ATPG bit-stream applied to input 9 of circuit s5378 Theoretical random noiselevel (16) 13th VLSI Design and Test Symposium

9. Effect of Noise • Noise inserted in ATPG vectors, generated for a sample of faults (RTL faults), for s5378 circuit, using increasing spectral threshold (ST) values (i.e., increasing noise) • 226 ATPG vectors for1602 RTL faults Gate-level faults detected by 226 ATPG vectors More faults detected than original vectors 13th VLSI Design and Test Symposium

10. BIST Architecture Weighted random bit-stream (W=0.5) Weighted random bit-stream (W=0.5) Proportion: SC1 = 0.5 SC2 = 0.5 Bit-stream of spectral component SC1 Noise inserted bit-stream Proportion: SC1 = 0.25 SC2 = 0.25 SC3 = 0.5 SC2 Weighted random bit-stream (W = 0.25) SC3 System clock To CUT Cellular Automata Register with AND-OR gates N-bit counter with XOR gates BIST clock Hadamard wave generator Weighted pseudo-random pattern generator 2 Spectral component synthesizer Input 1 System clock 3 BIST clock To CUT 1 Input 2 Randomizer 1 Hadamard Components Input 3 1 Weighted pseudo-random bit-streams 13th VLSI Design and Test Symposium

11. Hadamard Wave Generator 3-bit down counter; N flip-flops For H(N) Logic ‘1’ W0 LSB FF1 W1 CLK FF2 W2 W3 W 4 FF3 MSB W5 W6 W7 C. K. Yuen, “New Walsh-Function Generator,” Electronics Letters, vol. 7, p. 605, 1971. 13th VLSI Design and Test Symposium

12. Generation of Weighted Random Bit-streams Cellular Automata Register M Flip-flops P1=0.5 P1=0.25 P1=0.625 P1=0.5 P1=0.5 P1=0.5 P1=0.75 P1=0.875 P1=0.5 P1=0.9375 P1=0.5 P1=0.5 13th VLSI Design and Test Symposium

13. Spectral BIST Results and Area Overhead Test coverage results without reseeding (64000 vectors) Area overhead comparison 13th VLSI Design and Test Symposium

14. Test Coverage vs Number of Vectors 13th VLSI Design and Test Symposium

15. Test Coverage vs Number of Vectors 13th VLSI Design and Test Symposium

16. Reseeding of Spectral TPG Spectral BIST / Decompressor BIST / Decompressor Logic Flip-flops Data from external tester To CUT Parallel interface Serial scan interface 13th VLSI Design and Test Symposium

17. Spectral TPG Results with Reseeding Comparison of test data volume and test time for c7552 † assuming tester clock period Ttester=10ns and on-chip system clock period Tclk=1ns 13th VLSI Design and Test Symposium

18. Spectral TPG Results with Reseeding Comparison of test data volume and test time for s15850 (combinational) † assuming tester clock period Ttester=10ns and on-chip system clock period Tclk=1ns 13th VLSI Design and Test Symposium

19. Conclusion • Proposed a TPG design methodology for combinational circuits using spectral techniques. • Also proposed a reshuffling algorithm to enhance spectral components. • Designed TPG exhibits the following: • Higher test coverage than random and weighted random vectors for equal number of test vectors. • Encouraging test data compression capabilities up to 95%. • An order of magnitude reduction in test application time. • Issues to address: • Slightly high area overhead • Overhead might reduce by: • Implementation on larger circuits • Optimum selection of spectral components by reshuffling algorithm • Increase in test time for parallel HBM • Optimum seeds and intervals for reseeding can reduce the test time. 13th VLSI Design and Test Symposium

20. Thank you. Questions please? 13th VLSI Design and Test Symposium

21. Pre-processing of Test Vectors Reshuffling Algorithm: Input Data and Parameters: NI: No of inputs NV: No. of vectors V(1:NV,1:NI): Test vector Set of dimensions NV x NI hd: Dimension of Hadamard matrix H: Hadamard transform matrix of dimension 2hdx 2hd Procedure: Vector set V appended with redundant vectors to make weighting of bit-streams of all inputs = 0.5 for i=1 to NI Perform spectral analysis on bit-stream of input i: S = V(:,i) x H; Pick the prominent spectral component Sp(i) from S Rearrange vector set V such that maximum bits in the bit- streams of inputs 1 to i match with the picked prominent spectral components Sp(1 to i) respectively. end 13th VLSI Design and Test Symposium