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OpAmp OTA Design

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OpAmp OTA Design

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    1. OpAmp (OTA) Design The design process involves two distinct activities: Architecture Design Find an architecture already available and adapt it to present requirements Create a new architecture that can meet requirements Component Design Design transistor sizes Design compensation network

    5. Two Stage Op Amp Architecture

    10. Types of Compensation Miller - Use of a capacitor feeding back around a high-gain, inverting stage. Miller capacitor only Miller capacitor with an unity-gain buffer to block the forward path through the compensation capacitor. Can eliminate the RHP zero. Miller with a nulling resistor. Similar to Miller but with an added series resistance to gain control over the RHP zero. Self compensating - Load capacitor compensates the op amp (later). Feedforward - Bypassing a positive gain amplifier resulting in phase lead. Gain can be less than unity.

    11. General Miller effect

    23. Possible design steps for max GB For a given CL and Itot Assume a current share ratio q, i.e. I6+I5 = Itot, I5 = qI6 , I1 = I2 = I5/2 Size W6, L6 to achieve max gm6/(CL+Cgs6) which is > w2 C1 ? W6*L6, gm6 ? (W6/L6)0.5 Size W1, L1 so that gm1 ˜ 0.1gm6 this make z1 ˜ 10*GBW Select CC to achieve required PM by making gm1/CC < 0.5 w2 Check slew rate: SR = I5/CC Size M5, M7, M3/4 for current ratio, IMCR, etc

    24. Comment If we run the same total current Itot through a single stage common source amplifier made of M6 and M7 Single pole go/CL Gain gm6/go Single stage amp GB = gm6/CL >gm6/(CL+C1) > w2 > gm1/CC = GB of two stage amp Two stage amp achieves higher gain but speed is much slower! Can the single stage speed be recovered?

    25. Other considerations Output slew rate: SR = I5/CC Output swing range: VSS+Vdssat7 to VDD – Vdssat6 Min ICM: VSS + Vdssat5 + VTN + Von1 Max ICM: VDD - |VTP| - Von3 + VTN Mirror node approx. pole/zero cancellation Closed-loop pole stuck near by Can cause slow settling

    27. Eliminating RHP Zero at gm6/CC

    34. With the same CC as before Z1 cancels p2 P3, z3, z2, not affected P1 not affected much Phase margin drop due to p2 and z1 nearly removed Overall phase margin greatly improved Effects of other poles and zero become more important Can we reduce CC and improve GB?

    36. Increasing GB by using smaller CC It is possible to reduce CC to increase GB if z1/p2 pole zero cancellation is achieved Can extend to gm6/CL Or even a little bit higher But cannot push up too much higher Other poles, zeros Imprecise mirror pole/zero cancellation P2/z1 cancellation GB cannot be too high relative to these p/z cancellation Z2, z4, and pz=-1/RZCC must be much higher than GB

    37. Possible design steps for max GB For a given CL and Itot Assume a current share ratio q, i.e. I6+I5 = Itot, I5 = qI6 , I1 = I2 = I5/2 Size W6, L6 to achieve max single stage GB1 = gm6/(CL+Coutpara) Make z4=gm6/Cgd6 > (10~50)GB1 Choose GB = aGB1, Choose CC to make p2 ˜ GB/(10~20) Size W1, L1 and adjust q so that gm1/CC ˜ GB Make z2=gm2/Cgd2 > (10~20)GB Size Mz so that z1 cancels p2 Make sure |pz| due to Mz and CC >> GB Make sure PM at f=GB is sufficient Size M3/4 so that gm3/CM is > GB/(10~20) Check slew rate, and size other transistors for ICMR, OSR, etc

    38. Simple transistor circuits Can use any # of ideal current or voltage sources, resisters, and switches Use one or two transistors Examine various ways to place the input and output nodes Find optimal connections for high gain high bandwidth high or low output impedance low input referred noise

    39. Single transistor configurations It’s a four terminal device Three choices of input node For each input choice, there are two choices for the output node The other two terminals can be at VDD, GND, virtual short (V source), virtual open (I source), input, or output node Most connections are non-operative or duplicates D and S symmetric; B not useful

    45. Building realistic circuits from simple connections

    49. two transistor connections Start with one T connections, and add a second T Many possibilities many useless some obtainable by flip and combine from one T connections some new two T connections Search for ones with special properties in terms of AV, BW, ro, ri, etc

    50. First MOST is CS

    54. D1 connects to S2

    65. D1 connects to G2, two stages

    73. connecting S1 to G2

    76. connecting S1 to S2

    78. connecting S1 to D2

    80. M1 is common gate: D1 connects to G2

    81. D1 connects to S2

    82. PSRR

    86. Similar computation for PSRR-

    87. Two-Stage Cascode Architecture Why Cascode Op Amps? Control the frequency behavior Increase PSRR Simplifies design Where is the Cascode Technique Applied? First stage - Good noise performance Requires level translation to second stage Requires Miller compensation Second stage - Self compensating Reduces the efficiency of the Miller compensation Increases PSRR

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