Virtual memory

1. Virtual memory Titov Alexander 6.03.2010

2. Computer memory control output datapath processor input Classic components of a computer

3. Mapping from a virtual to a physical address Virtual address 31 30 29 28 27 . . . . . . . . . . . . . . . . . 15 14 13 12 11 10 9 8 . . . . . . . 3 2 1 0 Virtual page number Page offset Translation 29 28 27 . . . . . . . . . . . . . . . . . 15 14 13 12 11 10 9 8 . . . . . . . 3 2 1 0 Physical page number Page offset Physical address

4. 18 12 20 Page table Page table register Virtual address 31 30 29 28 27 . . . . . . . . . . . . . . . . . 15 14 13 12 11 10 9 8 . . . . . . . 3 2 1 0 Virtual page number Page offset Valid Physical page number Page table If 0 then page is not present in memory 29 28 27 . . . . . . . . . . . . . . . . . 15 14 13 12 11 10 9 8 . . . . . . . 3 2 1 0 Physical page number Page offset Physical address

5. Translation-lookaside buffer (TLB) Virtual page number Physical page address Tag Valid Physical memory Physical page or disk address Valid Disk storage

6. 32 2 18 12 20 16 12 Virtual address 31 30 29 28 27 . . . . . . . . . . . . . . . . . 15 14 13 12 11 10 9 8 . . . . . . . 3 2 1 0 Virtual page number Page offset Valid Dirty Tag Physical page number TLB = TLB hit = = = = = Physical page number Page offset Physical address Physical address tag Cache index Byte offset Cache Data Valid Tag Cache hit = Data

7. Processing a request through TLB and cache Virtual address TLB access TLB hit? TLB miss exception Yes No Physical address Write? No Yes Write access bit on? Try to read data from cache No Yes Write protection exception Write data into cache, update the tag, and put the data and the address into the write buffer Cache hit? Yes No Cache miss stall Deliver data to the CPU