William Stallings Computer Organization and Architecture 7 th Edition

1. William Stallings Computer Organization and Architecture7th Edition Chapter 3 System Buses

2. What is a program? • A sequence of steps • For each step, an arithmetic or logical operation is done • For each operation, a different set of control signals is needed

3. Program Concept • Hardwired systems are inflexible • General purpose hardware can do different tasks, given correct control signals • Instead of re-wiring, supply a new set of control signals

4. Hardwired Program • The process of connecting the various components in the desired configuration as a form of programming . The resulting program is in the form of hardware and is termed as ‘hardwired program’.

5. Function of Control Unit • For each operation a unique code is provided • e.g. ADD, MOV • A hardware segment accepts the code and issues the control signals • We have a computer!

6. Components • The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit • Data and instructions need to get into the system and results out • Input/output • Temporary storage of code and results is needed • Main memory

7. Computer Components:Top Level View

8. Register: • Program Counter: It contains the address of next instruction to be executed • Instruction Register: It holds the instruction i.e. currently being executed(Contains 8 bit opcode) • Memory Address Register: Hold the address of location to or from data is to be transferred • Memory Buffer Register: It contains data to be written in to or read out of address location • I/O Register: It specifies the particular I/O device • I/O Buffer Register: Used for exchange of data b/w Input/ Output module & CPU. • Accumulator:Temporary hold the operand and results of ALU operations

9. Program Execution: • Processor reads (fetches) instructions from memory one at a time and execute each instruction. • Program execution consist of repeating the process of instruction fetch and instruction execution • Instruction execution may involve several operation depends on the nature of instruction.

10. Instruction Cycle • Processing required for Instruction is called Instruction Cycle. • Two steps: • Fetch: • Execute

11. Fetch Cycle • Program Counter (PC) holds address of next instruction to fetch • Processor fetches instruction from memory location pointed to by PC • Increment PC • Unless told otherwise • Instruction loaded into Instruction Register (IR) • Processor interprets instruction and performs required actions

12. Execute Cycle • Processor-memory • data transfer between CPU and main memory • Processor- I/O • Data transfer between CPU and I/O module • Data processing • Some arithmetic or logical operation on data • Control • Alteration of sequence of operations • e.g. jump • Processor fetches an instruction from location 149 which specifies next instruction from location 182 thus on next fetch cycle , instruction will be fetched from location 18

13. Example of Program Execution

14. Instruction Cycle State Diagram

15. Instruction Address Calculator: Determines the address of next instruction to be executed. • Instruction Operating Decoding : Analyze instruction to determine type of operation to be performed and operand (if any) to be used. • Instruction Fetch: Read instruction from its memory location to CPU. • Operand Address Calculator: If the operation involves to an operand in memory or through peripherals then determines the address of operands. • Operand Fetch: Fetches the operand from memory & input device. • DataOperations :Perform the operation as indicated in the instruction. • Operand Stores: Write the result in memory or Output device.

16. Interrupts • Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing • Interrupts are provided to improve the processing efficiency.

17. Classes of Interrupts : • Program: Generated by some condition that occurs as a result of an instruction execution such as • e.g. overflow, division by zero , illegal machine instruction etc • Timer • Generated by internal processor timer • Used in pre-emptive multi-tasking • I/O • Generated by an I/O controller • To signal normal completion of an operation or to signal a variety of error conditions. • Hardware failure: Generated by a Power failure or memory parity error

18. Interrupt Cycle • Added to instruction cycle • Processor checks for interrupt • Indicated by an interrupt signal • If no interrupt, fetch next instruction • If interrupt pending: • Suspend execution of current program • Save context • Set PC to start address of interrupt handler routine • Process interrupt • Restore context and continue interrupted program

19. Transfer of Control via Interrupts

20. Instruction Cycle with Interrupts

21. Instruction Cycle (with Interrupts) - State Diagram

22. Multiple Interrupts • Disable interrupts • Processor will ignore further interrupts whilst processing one interrupt • Interrupts remain pending and are checked after first interrupt has been processed • Interrupts handled in sequence as they occur • Define priorities • Low priority interrupts can be interrupted by higher priority interrupts • When higher priority interrupt has been processed, processor returns to previous interrupt

23. Multiple Interrupts - Sequential

24. Multiple Interrupts – Nested

25. Time Sequence of Multiple Interrupts

26. Connecting All the units must be connected • Different type of connection for different type of unit • Memory • Input/Output • CPU • The collection of path connecting the various modules is called the Inter connection structure • The design of this structure will depend on the exchanges that must be made between modules. • Different type of exchanges discussed in next slide

27. Computer Modules

28. Memory Connection • Receives and sends data • Receives addresses (of locations) • Receives control signals • Read • Write • Timing

29. Input/Output Connection(1) • Similar to memory from computer’s viewpoint • There are external data path for the input and output of data with an external device, so, I/O may be able to send interrupt signals to processor. • Output • Receive data from computer • Send data to peripheral • Input • Receive data from peripheral • Send data to computer

30. Input/Output Connection(2) • Receive control signals from computer • Send control signals to peripherals • e.g. spin disk • Receive addresses from computer • e.g. port number to identify peripheral • Send interrupt signals (control)

31. CPU Connection • Reads instruction and data • Writes out data (after processing) • Sends control signals to other units • Receives (& acts on) interrupts

32. Types of transfer(Interconnection Structure) • Memory to Processor (Read):Processor reads an instruction or a unit of data from memory • Processor to Memory(Write): Processor writes a unit of data to memory • I/O to Processor(Read):Processor reads the data from an I/O device via I/O module • Processor to I/O(Write): Processor sends the data to the I/O device • I/O to or from Memory: For these two cases an I/O module is allowed to exchange data directly with memory.

33. What is BUS: • A group of wires that connects the several devices or • Communication pathway between two or more devices • Usually broadcast • Often grouped • A number of channels in one bus • e.g. 32 bit data bus is 32 separate single bit channels • Power lines may not be shown

34. SYSTEM BUS: • A bus that connects the major system module is called system bus (e.g. CPU I/O , Memory) • Bus consist of multiple communication pathway, or lines • A sequence of binary digit can be transmitted across a line. • For e.g. (8bit unit of data can be transmitted over 8 bus lines)

35. Bus Structure • A system bus consist, typically about 50 to hundred of separate lines. • Each line is assigned a particular meaning or function • There are a number of possible interconnection systems • On any bus each line is classified in to three functional groups: Control lines/Address lines/Data lines • In addition there may be power distribution lines that supply power to the attach modules.

36. Data Bus • Carries data : Provide path for moving data between modules • Remember that there is no difference between “data” and “instruction” at this level • Width is a key determinant of performance • Data bus consist of from 32 to hundreds of separate lines,(the number of lines being referred as a width of data bus • 8, 16, 32, 64 bit

37. Address bus • Identify the source or destination of data • e.g. CPU needs to read an instruction (data) from a given location in memory • Bus width determines maximum memory capacity of system • e.g. 8080 has 16 bit address bus giving 64k address space

38. Control Bus • The control line is used to control the access to and the use of data and address lines • Control and timing information: Timing signal indicates the validity of data and address information • read/write signal • Interrupt request • Clock signals • Typical control lines include the following: • Memory Write: Causes data on the bus to be written into the addressed location. • Memory Read: Causes data from the addressed location to be placed on the bus • I/O Read: : Causes data from the addressed I/O port to be placed on the bus. • I/O Write Causes data on the bus to be output to the addressed I/O port

39. Transfer ACK :Indicates that data have been accepted from or placed on the bus • BUS Request:Indicates that a module needs to gain control of the bus • Bus Grant: Indicate that a requesting module has been granted control of the bus • Interrupt Request: Indicate a Interrupt is pending • Interrupt ACK: Acknowledges that the pending interrupt has been recognized • Clock: Used to synchronized operation • Reset: Initialize all modules.

40. Single Bus Problems • Lots of devices on one bus leads to: • Propagation delays • Long data paths mean that co-ordination of bus use can adversely affect performance • If aggregate data transfer approaches bus capacity • Most systems use multiple buses to overcome these problems

41. Elements of Bus Design Bus Type Data Transfer Type • Dedicated Read • Multiplexed Write Method of Arbitration Read-Modify-Write • Centralized Read-After-Write • Distributed Block Timing • Synchronous • Asynchronous Bus Width • Address • Data

42. Bus Types Bus line can be separated in two generic types: • Dedicated • Separate data & address lines • Multiplexed • The method of using same line for multiple purposes is known as time multiplexing • Shared lines • Address valid or data valid control line • Advantage - fewer lines Save space & cost • Disadvantages • More complex control • Ultimate performance(Events that share same lines can not take place in parallel)

43. Bus Arbitration • More than one module may need to control the bus e.g. CPU and DMA controller • Only one module may control bus at one time • Arbitration may be: Centralized: A single hardware device referred to as bus controller ,and responsible for allocating time on bus. Distributed: No central controller each module contain access, control logic and module act together to share the bus. With both methods of arbitration. The purpose is to designate one device, either the processor or an I/O module,master.The Master may initiate a data transfer(e.g. Read or write) with some other device which act as a slave for this particular exchange.

44. Centralised or Distributed Arbitration • Centralised • Single hardware device controlling bus access • Bus Controller • Arbiter • May be part of CPU or separate • Distributed • Each module may claim the bus • Control logic on all modules

45. Timing • Co-ordination of events on bus Buses use either • Synchronous • Events determined by clock signals • Control Bus includes clock line • A single 1-0 is a bus cycle or clock cycle & defines a time slot. • All devices can read clock line • Usually sync on leading edge • Usually a single cycle for an event

46. Synchronous Timing Diagram

47. Synchronous Read & Write Read • For Read Operation process issue a read command at a start of second cycle • Memory module recognizes the address and after a delay of one cycle places a data and drops the read signal. Write: • For a Write Operation processor puts the data on the start of the second cycle . • Issues a write command after a data line have stabilize • Memory module copies the data from data line during third cycle.

48. Asynchronous Timing – Read Diagram

49. Asynchronous Read & Write Asynchronous: • The occurrence of events on a bus follows and depend on the occurrence of a previous events • It uses the control signal to indicate the validity Of the data and address on the bus it is called hand shaking Read: • Processor placed the address and status signal on the bus. • Issues a read command indicating the presence of valid address and control signals • Appropriate memory decodes the address and respond by placing the data on data line • Memory assets the acknowledged line to signal the processor that data is available • After reading the data it deasserts the read signal.

50. Asynchronous Read & Write • Memory module drop the data and acknowledge lines • Once the acknowledge line is dropped the master removes the address information. • Write • Process place the data at the same time that is put signal on the status and address line • The memory module responds to the write command by copying the data from data lines and then asserting the acknowledge line. • CONCLUSION: • Synchronous timing is simpler to implement and test • Less flexible then asynchronous timing