Parametric Fault Isolation Tester

1. Parametric Fault Isolation Tester • Team Members: • Phuong Ho, Ben Schwarz, • Padmashree Patil, Gary Davis, • Nicholas Klein • Capstone 2014 • Sponsored by Intel • Advisor: Dr. Robert Daasch Strategy Results Problem Statement • Design Universal Backplane PCB: • Enables connectivity to test equipment. • Allows for JTAG support of the part. • Design for useful life of > 6 years. • Smallest possible footprint • Fault isolation methodologies at Intel Corporation currently rely on using more than one testing with varying degrees of success and associated costs. These solutions have various components attached to Intel microprocessor pins which can cause moving the Unit Under Test (UUT) to other test equipment difficult. Moving the UUT between equipment has the potential to introduce error into the fault isolation. A low cost, all encompassing tester is needed. A total system solutionthat not only decreases required test time but reduces cost of testing. [LabView pic of GUI] Proposed Solution • Develop Tester Interface Unit: • Universal Backplane PCB • Product Specific Family PCB • Interconnection Cables • Develop Automated National Instruments LabView Tests: • Board ID • Boot Up • Standard Test Pins • Curve Tracing • Shorts and Opens • Latch Up • FLIR Image Capture • Automated Report Generation • Design Product specific family PCB: • Specific to each family of Intel Silicon • Sandy Bridge, Broadwell, etc. • Breaks out small pitch pins of microprocessor to common interface. • Socket able such that you can test multiple products with one board. • [Pic of how overall system set up] • Some paragraph about why this solution is so great. • Automated and comprehensive FI tester with significantly reduced throughput time and expenses. • This project will extend the capability of current FI across all product lines. • Some paragraph about Intel and PSUs collaboration. • PSU collaborates with Intel Corporation for senior student capstone projects. • Our group from PSU worked with PFI team to find the root cause in quality and reliability failure mechanisms in silicon products in the product development stage • Some paragraph about where our capstone will go after we’ve all left. • This project will be handled to Santa Clara Intel team after we left it. • All the required software and hardware user manual will be handled over to them. • Design a set of automated LabView Tests • User friendly GUI • Automated tests as well as user controlled options. • All test performed from one test station • Large main program is composed of smaller blocks Department of Electrical and Computer Engineering