Parametric Fault Isolation Tester

1. Parametric Fault Isolation Tester • Capstone 2014 • Sponsored by Intel • Advisor: Dr. Robert Daasch • Team Members: • Phuong Ho, Benjamin Schwarz, • Padmashree Patil, Nicholas Klein, Gary Davis Problem Statement Strategy Results • Design Universal Backplane PCB: • Research • Block Diagram Creation • Cadence Orcad Schematic • Cadence Allegro PCB Fault isolation methodologies at Intel currently rely on using more than one solution with varying degrees of success and associatedcosts. • These solutions have active/passive components attached to most pins which makes it difficult to perform accurate 4 quadrant testing and prevent interactive ESD. They also require some level of functionality to perform testing.  • A low cost, all encompassing tester is needed. Proposed Solution • Develop Tester Interface Unit: • Universal Backplane PCB • Product Specific Family PCB • Interconnection Cables • Develop Automated National Instruments LabView Tests: • Board ID • Boot Up • Standard Test Pins • Curve Tracing • Short on Power • Latch Up • FLIR Image Capture • Automated Report Generation Department of Electrical and Computer Engineering