A look at interrupts

1. A look at interrupts What are interrupts and why are they needed in an embedded system? Equally as important – how are these ideas handled on the Blackfin

2. Dispatch_Tasks ( )

3. The “standard” instruction cycleof a microprocessor (ENCM369) DECODE THE INSTRUCTION AND FETCH ANY VALUES NEEDED FROM REGISTER OR MEMORY RESETTHE PROCESSOR RESET*INTERRUPT(ACTIVE low) FETCH AN INSTRUCTION FROM PROGRAM MEMORY WRITE BACK THE ANSWER EXECUTE THE INSTRUCTION PROCESSOR RESET* +5V +5V RC time constant200 ms on68K GROUND

4. The “standard” instruction cycle DECODE THE INSTRUCTION AND FETCH ANY VALUES NEEDED FROM REGISTER OR MEMORY RESETTHE PROCESSOR RESET*(ACTIVE low) FETCH AN INSTRUCTION FROM PROGRAM MEMORY WRITE BACK THE ANSWER EXECUTE THE INSTRUCTION EXECUTING‘YOUR PROGRAM’ UNTIL POWER IS REMOVED

5. The “standard” instruction cyclewith external device having important data DECODE THE INSTRUCTION AND FETCH ANY VALUES NEEDED FROM REGISTER OR MEMORY RESETTHE PROCESSOR RESET*(ACTIVE low) FETCH AN INSTRUCTION FROM PROGRAM MEMORY WRITE BACK THE ANSWER EXECUTE THE INSTRUCTION This is the data 16-bits Checkifready EXTERNAL HARDWARE Control signal – ThanksData received Control signal – I have data for you

6. The “wait till ready” approach of reading data from external device In decode phase – read control register value In execute phase – check if 1 -- keep waiting (fetch-decode-execute-writeback instruction cycle) until the control value changes from 0 (device not ready) to 1 (device ready) When 1 – go to a different part of your program code to read the datae.g. call ReadData( ) Then your program must send an acknowledge back to device that the data has been read. e.g. call AcknowledgeReadData( ). The device can then go and get more values for you. PROBLEM: You have no time to do anything else other than wait Not a problem if waiting for this device is the only thing you want to do with the processor

7. Wait till ready approachVery problematic if many devices DECODE THE INSTRUCTION AND FETCH ANY VALUES NEEDED FROM REGISTER OR MEMORY RESETTHE PROCESSOR RESET*(ACTIVE low) FETCH AN INSTRUCTION FROM PROGRAM MEMORY WRITE BACK THE ANSWER Checkifready EXECUTE THE INSTRUCTION Checkifready Checkifready 16-bits 16-bits EXTERNAL HARDWARE EXTERNAL HARDWARE 16-bits Checkifready WAITS TOO LONG EXTERNAL HARDWARE

8. The “Poll approach” of getting dataNot much waiting – but a lot of “doing” read control register value of device 1 -- if 1 go to a different part of the code to “read the data” (ReadData1( ) ) – after reading the data send an acknowledge signal back to device 1 (AcknowledgeReadData1( ) ) -- if 0 go and read the control value of device 2 – don’t worry about device 1 for some time read control register value of device 2 -- if 1 go to a different part of the code to “read the data” (ReadData2() ) – after reading the data send an acknowledge signal back to device 2 (AcknowledgeReadData2( ) ) -- if 0 go and read the control value of device 3 – don’t worry about device 2 and 3 for some time ETC PROBLEM: What happens if, while you are handling device 2, device 1 has “time sensitive information” that will disappear if device 1 is not serviced immediately

9. Interrupt Approach – basic ideaExtra “phase” in instruction cycle DECODE THE INSTRUCTION AND FETCH ANY VALUES NEEDED FROM REGISTER OR MEMORY RESETTHE PROCESSOR RESET*(ACTIVE low) FETCH AN INSTRUCTION FROM “NORMAL”(NOT ISR) PROGRAM MEMORY NO WRITE BACK THE ANSWER CONTINUEAS BEFORE CHECK IF ANINTERRUPT REQUEST HAS OCCURRED EXECUTE THE INSTRUCTION yes CONTROL SIGNALDATA READY SIGNALBECOMES INTERRUPTREQUEST DOISR 16-bits data Acknowledge Request done EXTERNAL HARDWARE

10. Issues that MUST be solvedif using interrupts on a real uP • What if device hardware can only provide a “quick” I am ready signal? • What if more than one hardware device wants to send an interrupt request? • What if the programmer wants to “ignore” “low priority” interrupt requests? • What if certain interrupt requests are too important to ignore?

11. What if hardware device can only provide a “quick” I am ready signal?Add interrupt (capture) latch to processor CONTINUEAS BEFORE CHECK IF ANINTERRUPT REQUEST HAS OCCURRED DOISR yes Interrupt Latch (Capture Request) Processorclock signal causes loadof the latch to capturethe transient interrupt Interrupt Buffer 16-bits CONTROL SIGNALFAST CHANGINGDATA READY SIGNALSignal send (1) and then becomes 0 Acknowledge done EXTERNAL HARDWARE

12. What if the programmer wants to “ignore” a “low priority” interrupt?Add (Ignore) Interrupt Mask Interrupt Latch (Capture) CONTINUEAS BEFORE e.g. IGNORE INTERRUPT IF FIO_MASK_ABIT is 0 CHECK IF ANINTERRUPT REQUEST HAS OCCURRED DOISR yes Interrupt MaskIgnore Processorclock signal causes loadof the latch to capturethe transient interrupt Interrupt Buffer 16-bits CONTROL SIGNALDATA READY SIGNALBECOMES INTERRUPTREQUEST LINE Acknowledge done EXTERNAL HARDWARE

13. What if certain hardware interrupts are too important to ignore?NMI bypass the IGNORE Interrupt Mask CONTINUEAS BEFORE CHECK IF ANINTERRUPT REQUEST HAS OCCURRED Interrupt Latch (Capture) DOISR yes Interrupt MaskIgnore Processorclock signal causes loadof the latch to capturethe transient interrupt Interrupt Buffer 16-bits CONTROL SIGNALDATA READY SIGNALBECOMES INTERRUPTREQUEST LINE Acknowledge done EXTERNAL HARDWARE

14. What if more than one hardware wants to send an interrupt? Pending interrupts(still to be done CONTINUEAS BEFORE CHECK IF ANINTERRUPT REQUEST HAS OCCURRED Interrupt Latch (Capture) DOISR yes Interrupt MaskIgnore Processorclock signal causes loadof the latch to capturethe transient interrupt Interrupt Buffer 16-bits CONTROL SIGNALDATA READY SIGNALBECOMES INTERRUPTREQUEST LINE Acknowledge done EXTERNAL HARDWARE

15. Blackfin MASKS and LatchesSame hardware in concept

16. Using“idle”low power mode in Lab. 2

17. Normal “linear flow”PC increments to next instruction Use program counter PC as an Instruction Pointer registerFetch instruction at memory locationPC then increment the PC to point atthe next instruction PC = PC+2 PC = PC + 4;

18. Subroutine call flow PC = PC + 2 CALL INSTRUCTION DOESRETS = PC + 4 (FFA03C78) PC set to 0xFFA01E24So instruction 0xFFA01E24 done next This instruction is NOT fetched (until end of subroutine) This instruction is now fetchedHAVE JUMPED TO SUBROUTINE

19. Interrupt occurs HEREMust Jump to ISR NOW– but how? Use program counter PC as an Instruction Pointer registerFetch instruction at memory locationPC then increment the PC to point atthe next instruction PC = PC+2 PC = PC + 4;

20. First step is obvious PC has 0xFFA01E44 in it – Just about to fetch P0.L = instruction Remember what instruction you were about to execute – so you can do that instruction after finishing the ISR RETI is “register used to remember the instruction “stopped” by interrupt RETI = PC (0xFFA01E44) PC now set to ????? value to make interrupt happen Interrupt occurs HERE (green arrow)Must Jump to ISR NOW – but how? How make this happen?

21. First step is obvious Remember what instruction you were about to execute RETI = PC (0xFFA01E44) PC = ????? Some how – like magic we must set PC = start of Timer ISR0xFFA01EC0then processor will start executing TimerISR code Interrupt occurs HEREMust Jump to ISR – but how

22. Solution – Blackfin has Lookup table of what value to put into PC for each interrupt than can occur Look-up table for the start of every interrupt routine is stored in EVR table Event vector register table Event (e.g interrupts) Table

23. Why are all these “event addresses” in the EVR (ISR jump) table the same? This is the address of the “the processor does not know what to do if there is an interrupt of this sort” EXCEPTION

24. The “don’t know what to do” “exception” service routine (ESR) • IDLE This is theassembly code While(wait till some happens) instruction VDSP Emulator puts in a “breakpoint” so for us the program stops. In real life – processor can’t “stop”, just goes into an infiniteloop until “watchdog timer” resets the processor

25. “Don’t know what to do”Exception • This exception hangs the processor • Keeps doing same instruction (doing nothing) which is safer than doing something • The developer should have provided a better ESR if had known what to do • Problem solved by using “WATCHDOG TIMER”

26. Solution – Lookup tableof what value to put into PC for each type of interrupt that occurs • Question – the start of the ISR is in the event table – How did it get there? Event (e.g interrupts) Table

27. The start address of the ISR got into the event table HOW? • Tell (register) the processor how to handle each interrupt service routine Also we can understand what the raise( ) C++ function does – This is a special C++ instruction to allow us to test ISR

28. Blackfin MASKS and Latches Raise( ) use “software to put a 1 into the interrupt latch register – making the processorthink that a hardware interrupt has happened

29. Event table information can be found in the Blackfin Hardware Manual

30. What happens if the device does take away its “I’m ready” signal during an interrupt? CONTINUEAS BEFORE CHECK IF ANINTERRUPT REQUEST HAS OCCURRED DOISR yes Interrupt Latch (Capture) Processorclock signal causes loadof the latch to capturethe transient interrupt Interrupt Buffer 16-bits CONTROL SIGNALDATA READY SIGNAL Acknowledge done EXTERNAL HARDWARE

31. Tackled today • Three ways of handling hardware requests for service • Wait till the device signals “ready”then process the data • If device 1 ready – process its data • Else If device 2 ready – process its data POLL • Interrupt – start processing the data from a “specific device NOW!