Sequential Statements

Sequential Statements Instructors: Fu-Chiung Cheng (鄭福炯) Associate Professor Computer Science & Engineering Tatung University

Sequential Statement • These statements can appear inside a process description : • variable assignments • if-then-else • Case • Loop • infinite loop • while loop • for loop • assertion and report • signal assignments • function and procedure calls

Sequential Statement-if • EBNF: if-statement • if_stmt <= • [ if_label : ] • if boolean_expr then • { sequential_stmt } • { elsif boolean_expr then • { sequential_stmt } } • [else • { sequential_stmt } ] • end if [ if_label ] ;

Sequential Statement-if • examples • if sel = 0 then • result <= input_0; -- executed if sel = 0 • else • result <= input_1; -- executed if sel /= 0 • end if; • more examples see sources

entity thermostat is port ( desired_temp, actual_temp : in integer; heater_on : out boolean ); end entity thermostat; -------------------------------------------------------------------- architecture example of thermostat is begin controller : process (desired_temp, actual_temp) is begin if actual_temp < desired_temp - 2 then heater_on <= true; elsif actual_temp > desired_temp + 2 then heater_on <= false; end if; end process controller; end architecture example;

Sequential Statement-case • EBNF:case_stmt <= • [ case_label : ] • case expr is • (when choices => { sequential_stmt } ) • { … } • end case [ case_label ] ; • choices <= ( simple_expr | discrete_range | • others ) {… }

Sequential Statement-case type alu_func is (pass1, pass2, add, sub); case func is when pass1 => res := op1; when pass2 => res := op2; when add => res := op1 + op2; when sub => res = op1 – op2; end case;

Sequential Statement-case type opcodes is (nop, add, sub, ld, st, jmp, br, halt); case opcode is when ld | add | sub => op := mem_op; when st | jmp => op := add_op; when others => op := 0; end case;

Sequential Statement-case type opcodes is (nop, add, sub, ld, st, jmp, br, halt); case opcode is when add to ld => op := mem_op; when br downto st => op := add_op; when others => op := 0; end case;

Sequential Statement-case • All possible values of the selector expression must be covered by one and only one choice • The values in the choices must be locally static, (known at analysis stage) • If the others choice is used, it must be the last alternative and the only choice in the alternative.

library ieee; use ieee.std_logic_1164.all; entity mux4 is port ( sel : in sel_range; d0, d1, d2, d3 : in std_ulogic; z : out std_ulogic ); end entity mux4; architecture demo of mux4 is begin out_select : process (sel, d0, d1, d2, d3) is begin case sel is when 0 => z <= d0; when 1 => z <= d1; when 2 => z <= d2; when 3 => z <= d3; end case; end process out_select; end architecture demo;

Sequential Statement-null • Case statement requires an alternative for every value. • Sometimes no action is required for a particular value. • No action is specified by a “null” statement • null_stmt <= [ label : ] null ; • Example: case opcode is when add => acc = acc + op; when sub => acc = acc – op; when nop => null; end case;

Sequential Statement-null • Define a process to be implemented later control_section : process ( sensitivity_list ) is begin null; end process control_section;

Sequential Statement-loop • VHDL provides three types of loop or iterative constructs: • infinite loop • while loop • for loop

Sequential Statement-loop • EBNF: Infinite loop infinite_loop_stmt <= [ loop_label : ] loop { sequential_stmt } end loop [ loop_label ] ;

entity counter is port ( clk : in bit; count : out natural ); end entity counter; architecture behavior of counter is begin incrementer : process is variable count_value : natural := 0; begin count <= count_value; loop wait until clk = '1'; count_value := (count_value + 1) mod 16; count <= count_value; end loop; end process incrementer; end architecture behavior;

Sequential Statement-exit • Exit statement can be used to “exit” or “jump out” of any loop. • EBNF: exit_stmt <= [label:] exit [ loop_label : ] [ when boolean_expr ] ; • Example: LoopName: loop … exit LoopName; … end loop;

Sequential Statement-loop with exit • nexted loop with exit statements OuterLoopName: loop … InnerLoopName: loop … exit OuterLoopName when cond-1; … exit when cond-2 … end loop InnerLoopName; …. exit OuterLoopName when cond-3 …. end loop OuterLoopName;

Sequential Statement-exit • Example: loop … exit ; -- jumps out of the inner most loop … end loop; …… -- exit causes the execution to start from this statement onwards

Sequential Statement-exit • More examples: exit loop1; -- jumps out of loop -- with label loop1 exit when x = 1; -- jumps out of inner -- most loop when -- condition is true

entity counter is port ( clk, reset : in bit; count : out natural ); end entity counter; -------------------------------------------------- architecture behavior of counter is begin -- counter process -- next page end architecture behavior;

incrementer : process is variable count_value : natural := 0; begin count <= count_value; loop loop wait until clk = '1' or reset = '1'; exit when reset = '1'; count_value := (count_value + 1) mod 16; count <= count_value; end loop; -- at this point, reset = '1' count_value := 0; count <= count_value; wait until reset = '0'; end loop; end process incrementer;

Sequential Statement-next • Causes the start of the next iteration of the loop • EBNF: next_stmt <= [ label : ] next [ loop_label ] [ when boolean_expr ] ; • Examples: loop A: ……… … next ; -- causes the execution to start from stmt label A B: …… -- statement B and those following it are skipped … end loop;

Sequential Statement-while • EBNF: while_loop_stmt <= [ loop_label : ] while boolean_expr loop { sequential_stmt } end loop [ loop_label ]; • Example:while index >0 loop -- do something with indexend loop;

entity cos is port ( theta : in real; result : out real ); end entity cos; architecture series of cos is begin summation : process (theta) is variable sum, term : real; variable n : natural; begin sum := 1.0; term := 1.0; n := 0; while abs term > abs (sum / 1.0E6) loop n := n + 2; term := (-term) * theta**2 / real(((n-1) * n)); sum := sum + term; end loop; result <= sum; end process summation; end architecture series;

Sequential Statement-for • EBNF: for_loop_stmt <=[ loop_label : ] for id in discrete_range loop { sequential_stmt }end loop [ loop_label ]; • discrete_range <= expr ( to | downto ) expr • Example:for count in 0 to 127 loopcount_out <= count;wait for 5 ns;end loop;

Sequential Statement-for • Example:type controller_state is (initial, idle, active, error);…for state in controller_state loop . . . -- loop parameter state is implicitly -- declared over the for loopend loop;

Sequential Statement-for • Illegal example:erroneous : process is variable i, j : integer; begin i := loop_param; -- error! (not defined) for loop_param in 1 to 10 loop loop_param := 5; -- error! (loop_param is constant) end loop; j := loop_param; -- error! (not defined) end process erroneous;

Sequential Statement-for • example:hiding_example : process is variable a, b : integer; begin a := 10; for a in 0 to 7 loop b := a; end loop; -- a = 10, and b = 7 . . . end process hiding_example;

Sequential Statement-for • Loop parameter’s type is the base type of the discrete range. • Loop parameter is a constant inside the loop body. • It can be used in an expression but not written to. • Loop parameter is not required to be explicitly declared. • Loop parameter’s scope is defined by the loop body. • Consequently, it hides any variable of the same name inside the loop body.

architecture fixed_length_series of cos is begin summation : process (theta) is variable sum, term : real; begin sum := 1.0; term := 1.0; for n in 1 to 9 loop term := (-term) * theta**2 / real(((2*n-1) * 2*n)); sum := sum + term; end loop; result <= sum; end process summation; end architecture fixed_length_series;

Sequential Statement-assertion • Assertion statements can be used to verify if a design functions correctly • Assert statements are particularly useful for debugging. • EBNF: assert_stmt <=[ label:] assert boolean_expr [ report expr ] [severity expr ] ; • Severity level: note, warning, error and failure • Default Severity: error

Sequential Statement-assertion • Examples:assert initialValue <= maxValue;assert value <= maxValue report “Value too large”;assert currentCharacter >= '0' and currentCharacter <= '9‘report "Input number " & input_string & " contains a non-digit";

Sequential Statement-assertion assert free_memory >= low_water_limitreport "low on memory, about to start garbage collect“severity note;assert packet_length /= 0report "empty network packet received“severity warning;assert clock_pulse_width >= min_clock_widthseverity error;assert (lastPosition - firstPosition + 1) = noOfEntriesreport "inconsistency in buffer model“severity failure;

entity SR_flipflop is port ( S, R : in bit; Q : out bit ); end entity SR_flipflop; architecture checking of SR_flipflop is begin set_reset : process (S, R) is begin assert S = '1' nand R = '1'; if S = '1' then Q <= '1'; end if; if R = '1' then Q <= '0'; end if; end process set_reset; end architecture checking;

maximizer : process (a, b, c) variable result : integer; begin if a > b then if a > c then result := a; else result := a; -- Oops! Should be: result := c; end if; elsif b > c then result := b; else result := c; end if; assert result >= a and result >= b and result >= c report "inconsistent result for maximum" severity failure; z <= result; end process maximizer;

Sequential Statement-report • EBNF: report_stmt <= [ label : ] report expr [ severity expr] ; • Useful for writing “trace writes” in VHDL • Example:report “writing data to output ports” • Default Severity: note

Sequential Statement-report transmit_element : process (transmit_data) is -- . . . -- variable declarations begin report "transmit_element: data = " & data_type'image(transmit_data); -- . . . end process transmit_element;

Naming Rule • Entity names: RegisterBank • Architecture names: BehaviorModel • Process Names: StoreAndCheck • Constants, Labels: CONTROL_SECTION • Function/procedure names: getMaxValue() • Variables and signals: returnValue • Keyword: ENTITY ... IS

Sequential Statements