Power Efficiency for Variation-Tolerant Multicore Processors

1. Power Efficiency for Variation-Tolerant Multicore Processors Authors :James Donald & Margret Martonosi 2006 Presented By Ruba Sultan

2. Abstract • This work introduce a design with appropriate options to ensure timing reliability while still meeting the appropriate performance and power requirements, in spite of process variation

3. Introduction • Process Variation: Statistical Description of natural fluctuation in process output in different times. • Process Variation is an ever increasing challenge in microprocessor design • Deep submicron technology pose significant risks in timing and also variation in leakage power • Post- silicon circuit technique applied to ensure valid timing but there still power leakage.

4. Used Techniques • Two techniques : • Adaptive Body Base (ABB) • Toggling an additional voltage between the base and the source this allows various timing paths to be sped up at the cost possibly significant leakage power increase. • VDD adjustment • These effects on core power occur on top of inherent variations in leakage power, which can vary significantly across cores

5. Methodology • An excess power cutoff values, ranging from 1 to 6 are used to estimate the amount of tolerable process variation for multicore to maximize the performance/watt. They used to decide when to turn off extra power-consuming cores. • PTCMP, a fast multicore simulation environment, is used to validate the analysis using multiprogrammed workloads • Equations are extended to the problem of parallel programming • 8 applications (benchmark) used in experiment simulation .

6. Conclusion • This work optimized the power and performance characteristics of multicore architecture when running multiprogrammed workloads and parallel applications in the face of process variations

7. Thank you