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III. Multicore Processors (6)

III. Multicore Processors (6). Dezső Sima Spring 2007. (Ver. 2.0).  Dezső Sima, 2007. 10.4. Sun’s MC processors. 10.4.1 Gemini. 10.4.2 UltraSPARC IV line. 10.4.3 UltraSPARC T line. 10.4 Evolution of Sun’s processor lines. Multi-core processors.

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III. Multicore Processors (6)

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  1. III. Multicore Processors (6) Dezső Sima Spring 2007 (Ver. 2.0)  Dezső Sima, 2007

  2. 10.4. Sun’s MC processors • 10.4.1 Gemini • 10.4.2 UltraSPARC IV line • 10.4.3 UltraSPARC T line

  3. 10.4 Evolution of Sun’s processor lines Multi-core processors Figure: Overview of Sun’s major processor families Source: Kapil S., „Gemini,” 2003, http://www.hotchips.org/archives/hc15/3_Tue/12.sun.pdf

  4. 10.4 Sun’s MC processors 10.4.1 Gemini • Gemini (cancelled) 130 nm 4/2004

  5. 10.4.1 Gemini (1) JBus contr. Mem. contr. Figure: The Gemini processor Source: Kapil S., „Gemini,” 2003, http://www.hotchips.org/archives/hc15/3_Tue/12.sun.pdf

  6. 10.4.1 Gemini (2) Figure: Block diagram and die shot of the Gemini Source: Kapil S., „Gemini,” 2003, http://www.hotchips.org/archives/hc15/3_Tue/12.sun.pdf

  7. 10.4.1 Gemini (3) Figure: Main features of the Gemini processor Source: Kapil S., „Gemini,” 2003, http://www.hotchips.org/archives/hc15/3_Tue/12.sun.pdf

  8. 10.4.1 Gemini (4) Model Gemini Dual/Quad-Core DC Cores 2* UltraSPARC II Introduction Cancelled 4/2004 Technology 130 nm Die size 206 mm2 Nr. of transistors 80 mtrs. fc [GHz] 1.0/1.2 L2 Size/allocation 2*512 KB/private Implementation On-die L3 Size Implementation Mem. Contr. On-die TDP [W] 32 Socket 959 pin PGA Multithreading Table: Main features of Sun’s Gemini

  9. 10.4 Sun’s MC processors 10.4.2 UltraSPARC IV line • UltraSPARC IV Jaguar 3/2004 130 nm • UltraSPARC IV+ Panther 9/2005 90 nm

  10. 10.4.2 UltraSPARC IV (1) ARB: Arbiter Figure : UltraSPARC IV (Jaguar) Source: C. Boussard: Architecture des processeurshttp://laser.igh.cnrs.fr/IMG/pdf/SUN-CNRS-archi-cpu-3.pdf

  11. 10.4.2 UltraSPARC IV (2) Figure: Floor plan of the UltraSPARC IV Source: Krewell K., „UltraSPARCIV Mirrors Predecessor, MPR, Nov. 10, 2003, http://www.sun.com/processors/feature/M45_UltraSPARC4_rpnt.pdf

  12. 10.4.2 UltraSPARC IV (3) Model Gemini UltraSPARC IV(Jaguar) Dual/Quad-Core DC DC Cores 2* UltraSPARC II 2*UltraSPARC III Introduction Cancelled 4/2004 7/2004 Technology 130 nm 130 nm Die size 206 mm2 352 mm2 Nr. of transistors 80 mtrs. 66 mtrs. fc [GHz] 1.0/1.2 1.050/1.200/1.350 L2 Size/allocation 2*512 KB/private 2*8 MB/private Implementation On-die Off-die, L2 tags on-die L3 Size 16 MB/shared Implementation Mem. Contr. On-die On-die TDP [W] 32 108 Socket 959 pin PGA 1368 pin LGA Multithreading Table: Main features of Sun’s UltraSPARC IV processor

  13. 10.4.2 UltraSPARC IV+ (1) Figure: UltraSPARC IV+ (Panther) Source: C. Boussard: Architecture des processeurs,http://laser.igh.cnrs.fr/IMG/pdf/SUN-CNRS-archi-cpu-3.pdf

  14. 10.4.2 UltraSPARC IV+ (2) UltraSPARC IV+ 19.7 x 17.0 mm Figure: Die shot and floor plan of the UltraSPARCIV+ Source: Dixit A. et al., „Implementation and Productization of a 4th Generation 1.8 GHz Dual-Core SPARC V9 Microprocessor, Febr. 2006, http://www.ewh.ieee.org/r6/scv/ssc/Feb2006.pdf

  15. 10.4.2 UltraSPARC IV+ (3) UltraSPARC IV+ UltraSPARC IV 130 nm/356 mm2/66 mtrs 90 nm/335 mm2/295 mtrs Figure: Contrasting the floor plans of the UltraSPARC IV and UltraSPARC IV+ dies Sources: Krewell K., „UltraSPARCIV Mirrors Predecessor, MPR, Nov. 10, 2003, http://www.sun.com/processors/feature/M45_UltraSPARC4_rpnt.pdf Dixit A. et al., „Implementation and Productization of a 4th Generation 1.8 GHz Dual-Core SPARC V9 Microprocessor, Febr. 2006, http://www.ewh.ieee.org/r6/scv/ssc/Feb2006.pdf

  16. 10.4.2 UltraSPARC IV+ (4) Figure: Schmoo plot of the UltraSPARCIV+ Source: Dixit A. et al., „Implementation and Productization of a 4th Generation 1.8 GHz Dual-Core SPARC V9 Microprocessor, Febr. 2006, http://www.ewh.ieee.org/r6/scv/ssc/Feb2006.pdf

  17. 10.4.2 UltraSPARC IV+ (5) Model Gemini UltraSPARC IV(Jaguar) UltraSPARC IV+(Panther) Dual/Quad-Core DC DC DC Cores 2* UltraSPARC II 2*UltraSPARC III 2*UltraSPARC III Introduction Cancelled 4/2004 7/2004 9/2005 Technology 130 nm 130 nm 90 nm Die size 206 mm2 352 mm2 335 mm2 Nr. of transistors 80 mtrs. 66 mtrs. 295 mtrs. fc [GHz] 1.0/1.2 1.050/1.200/1.350 1.5/1.8 L2 Size/allocation 2*512 KB/private 2*8 MB/private 2 MB/shared Implementation On-die Off-die, L2 tags on-die On-die L3 Size 16 MB/shared 32 MB/shared Implementation L3 tags on-die,L3 exclusive of L2 Mem. Contr. On-die On-die On-die TDP [W] 32 108 90 Socket 959 pin PGA 1368 pin LGA 1368 pin LGA Multithreading Table: Main features of Sun’s IV+ processor

  18. 10.4 Sun’s MC processors 10.4.3 UltraSPARC T line • UltraSPARC T1 Niagara 11/2005 90 nm • UltraSPARC T2 Niagara 2 2007 65 nm

  19. 10.4.3 UltraSPARC T1 (1) Figure: Block diagram of the UltraSPARC T1 (Niagara) Source: Laudon J., „UltraSPARC T1: A 32-threaded CMP for Servers, 2006, http://www.cs.duke.edu/courses/fall06/cps220/lectures/UltraSparc_T1_Niagra.pdf

  20. 10.4.3 UltraSPARC T1 (2) Figure: Pipeline stages of the Niagara cores (scalar FX cores) Source: Laudon J., „UltraSPARC T1: A 32-threaded CMP for Servers, 2006, http://www.cs.duke.edu/courses/fall06/cps220/lectures/UltraSparc_T1_Niagra.pdf

  21. 10.4.3 UltraSPARC T1 (3) Figure: Die shot of Niagara Source: Laudon J., „UltraSPARC T1: A 32-threaded CMP for Servers, 2006, http://www.cs.duke.edu/courses/fall06/cps220/lectures/UltraSparc_T1_Niagra.pdf

  22. 10.4.3 UltraSPARC T1 (4) Figure: Floor plan and main features of Niagara Source: Laudon J., „UltraSPARC T1: A 32-threaded CMP for Servers, 2006, http://www.cs.duke.edu/courses/fall06/cps220/lectures/UltraSparc_T1_Niagra.pdf

  23. 10.4.3 UltraSPARC T1 (5) Series UltraSPARC T1 Models UltraSPARC T1 Nr. of cores 8 cores Impl. or the cores Monolithic Architecture SPARC V9 Cores Scalar integer FX cores Introduction 11/2005 Technology 90 nm Die size 379 mm2 Nr. of transistors 279 mtrs. fc [GHz] 1.2 L2 Size/allocation 3 MB/shared Implementation On-die L3 I/O-bus JBus (3.2 GB/s) Interconnection NW Bandwidth: >200 GB/s Memory controller 4-channels, on-die, 400 MT/s Memory bandwidth 25.6 GB/s TDP [W] 63 Multithreading 4-way/core Table: Main features of Sun’s UltraSPARC T1 processor

  24. 10.4.3 UltraSPARC T2 (1) Figure: Block diagram of UltraSPARC 2 (Niagara-2) Source: Golla R, „Niagara2: A Highly Threaded Server-on-a-Chip,” Oct. 2006, http://www.opensparc.net/pubs/preszo//06/04-Sun-Golla.pdf

  25. 10.4.3 UltraSPARC T2 (2) Figure: block diagram of the cores in Niagara 2 Source: Golla R, „Niagara2: A Highly Threaded Server-on-a-Chip,” Oct. 2006, http://www.opensparc.net/pubs/preszo//06/04-Sun-Golla.pdf

  26. 10.4.3 UltraSPARC T2 (3) Figure: The full crossbar swith of Niagara 2 Source: Golla R, „Niagara2: A Highly Threaded Server-on-a-Chip,” Oct. 2006, http://www.opensparc.net/pubs/preszo//06/04-Sun-Golla.pdf

  27. 10.4.3 UltraSPARC T2 (4) Main features and floor plan of the Niagara-2 Source: Golla R, „Niagara2: A Highly Threaded Server-on-a-Chip,” Oct. 2006, http://www.opensparc.net/pubs/preszo//06/04-Sun-Golla.pdf

  28. 10.4.3 UltraSPARC T2 (5) Figure: Floor plan of the Niagara-2 Source: Grohoski G., „Niagara-2,” Aug. 2006, http://www.opensparc.net/pubs/preszo/06/HotChips06_09_ppt_master.pdf

  29. 10.4.3 UltraSPARC T2 (6) Figure: Comparison of the block diagrams of Niagara-1 and -2 Source: Kanter D.” Niagara II, The Hydra Returns,” http://realworldtech.com/page.cfm?ArticleID=RWT090406012516&p=4

  30. 10.4.3 UltraSPARC T2 (7) Series UltraSPARC T1/T2 Models UltraSPARC T1 UltraSPARC T2 Nr. of cores 8 cores 8 cores Impl. or the cores Monolithic Monolithic Architecture SPARC V9 SPARC V9 Cores Scalar integer FX cores Dual-issue FX/FP cores Introduction 11/2005 2007 Technology 90 nm 65 nm Die size 379 mm2 342 mm2 Nr. of transistors 279 mtrs. n.a. fc [GHz] 1.2 1.4 L2 Size/allocation 3 MB/shared 4 MB/shared Implementation On-die On-die L3 I/O-bus JBus (3.2 GB/s) JBus (3.2 GB/s) Interconnection NW Bandwidth: >200 GB/s Full 8*9 crossbar switch Memory controller 4-channels, on-die, 400 MT/s 4-channels, on-die, 400 MT/s Memory bandwidth 25.6 GB/s 42.7 GB/s TDP [W] 63 72 (est.) Multithreading 4-way/core 8-way/core Table: Main features of Sun’s UltraSPARC T2 processor

  31. 10.4 Literature (1) Gemini Kapil S., „Gemini,” 2003, http://www.hotchips.org/archives/hc15/3_Tue/12.sun.pdf UltraSPARC IV Boussard C., „Architecture des processeurs,” http://laser.igh.cnrs.fr/IMG/pdf/SUN-CNRS-archi-cpu-3.pdf Krewell K., „UltraSPARCIV Mirrors Predecessor, MPR, Nov. 10, 2003, http://www.sun.com/processors/feature/M45_UltraSPARC4_rpnt.pdf - „UltraSPARC IV Processor User’s Manual Supplement,” Ver. 1.0, Sun Microsystems, Apr. 2004, http://www.sun.com/processors/manuals/USIV_v1.0.pdf - UltraSPARC IV Processor Architecture Overview, Technical Whitepaper, Febr. 2004, http://www.sun.com/processors/whitepapers/us4_whitepaper.pdf UltraSPARC IV+ Boussard C.,„Architecture des processeurs,”,http://laser.igh.cnrs.fr/IMG/pdf/SUN-CNRS-archi-cpu-3.pdf Dixit A. et al., „Implementation and Productization of a 4th Generation 1.8 GHz Dual-Core SPARC V9 Microprocessor, Febr. 2006, http://www.ewh.ieee.org/r6/scv/ssc/Feb2006.pdf - „UltraSPARC IV+ Processor User’s Manual Supplement,” Ver. 1.0, Sun Microsystems, Oct. 2005, http://www.sun.com/processors/manuals/USIVplus_v1.0.pdf

  32. 10.4 Literature (2) UltraSPARC T1 Kongetira P., Aingaran K., Olukoton K., „Niagara: A 32-way Multithreaded SPARC Processor,” IEEE Micro, March-April 2005, pp. 21-29 Laudon J., „UltraSPARC T1: A 32-threaded CMP for Servers, 2006, http://www.cs.duke.edu/courses/fall06/cps220/lectures/UltraSparc_T1_Niagra.pdf - „UltraSPARC T1 Supplement to the UltraSPARC architecture 2005, Draft D2.0, March 2006, http://opensparc-t1.sunsource.net/specs/UST1-UASuppl-current-draft-P-EXT.pdf UltraSPARC T2 Golla R., „Niagara2: A Highly Threaded Server-on-a-Chip,” Oct. 2006, http://www.opensparc.net/pubs/preszo//06/04-Sun-Golla.pdf Grohoski G., „Niagara-2,” Aug. 2006, http://www.opensparc.net/pubs/preszo/06/HotChips06_09_ppt_master.pdf Kanter D.” Niagara II, The Hydra Returns,” http://realworldtech.com/page.cfm?ArticleID=RWT090406012516&p=4 McGhan H., „Niagara 2 Opens The Floodgates,” Microprocessor Report, Nov. 6, 2006, pp. 1-9

  33. 10.5. Fujitsu’s MC processors • SPARC64 VI • SPARC64 VII

  34. 10.5 Fujitsu’s MC processors Dual-core SPARC64 line • SPARC64 VI Olympus 90 nm 2007 Jupiter 65 nm • SPARC64 VII 2008

  35. 10.5 SPARC64 VI Reservation Stations (E: FX, F: FP, A: Adress, FP/SP: L/S) Execution Units (EX: FX, FL: PA, AGEN: Adr. Gen.) Figure: Block diagram of the SPARC64 VI Source:Inouo A., „Fujitsu SPARC64 VI, Fall Microprocessor Forum, Oct. 2006, Fujitsu Ltd., http://www.ssken.gr.jp/lib/nl/2006/sci/2/3_inouePPT_pre.pdf

  36. 10.5 SPARC64 VII (1) Figure: Block diagram of the SPARC64 VII Source:Inouo A., „Fujitsu SPARC64 VI, Fall Microprocessor Forum, Oct. 2006, Fujitsu Ltd., http://www.ssken.gr.jp/lib/nl/2006/sci/2/3_inouePPT_pre.pdf

  37. 10.5 SPARC64 VI/VII (2) Series SPARC64 Models SPARC64 VI (Olympus) SPARC64 VII (Jupiter) Cores 2*SPARC64V (enhanced) 4*SPARC64 VI (enhanced) Introduction 2007 2008 Technology 90 nm 65 nm Die size 421 mm2 464 mm2 Nr. of transistors 540 mtrs. n.A fc [GHz] 2.4 ~ 2.7 L2 Size/allocation 6 MB/shared 6 MB/shared Implementation On-die On-die L3 FSB [MT/s] Jupiter Bus Jupiter Bus TDP [W] 120 ~ 120 Multithreading 2-way 2-way Table: Main features of Fujitiu’s multi-core processors (superscalar RISC’s)

  38. 10.5 Literature Sparc64 line Inouo A., „Fujitsu SPARC64 VI,” Fall Microprocessor Forum, Oct. 2006, Fujitsu Ltd., http://www.ssken.gr.jp/lib/nl/2006/sci/2/3_inouePPT_pre.pdf Krewell K., „Fujitsu Makes SPARC See Double,” Microprocessor Report, Nov. 24, 2003, pp. 1-3 Krewell K., „SPARC’s Still Going Strong,” Microprocessor Report, Nov. 14, 2005, pp. 1-3 Maruyama T., „SPARC64 VI/VI+ Next Generation processor,” MPF, Oct. 2005, http://primeserver.fujitsu.com/primepower/event/report/pf-2005/pdf/mpf2005scr.pdf

  39. 10.6. HP’s MC processors • PA-8800 • PA-8900

  40. 10.6 HP’s dual-core processors Dual-core PA-8xxx processors (PA 8700-based) • PA-8800 Mako 130 nm 2/2004 Shortfin 130 nm • PA-8900 5/2005

  41. 10.6 PA-8800 (1) Figure: The underlaying PA-8700 core Source: E&M Computing, http://www.emet.co.il/events/amd/processors.pdf

  42. 10.6 PA-8800 (2) Figure: Block diagram of the PA-8800 Sources: Lostcircuits, Oct. 2001, http://www.lostcircuits.com/cpu/hp_pa8800/3dblock4.jpg Johnson D., „HP’s Mako processor”, Oct. 2001, ftp.parisc-linux.org/docs/whitepapers/mako_mpf_2001.pdf

  43. 10.6 PA-8800 (3) Figure: Floorplan of the Mako Source: Johnson D., „HP’s Mako processor”, Oct. 2001, ftp.parisc-linux.org/docs/whitepapers/mako_mpf_2001.pdf

  44. 10.6 PA-8800 (4) Figure: Contrasting the Floorplans of the PA-8700 and PA-8800 processors Sources: E&M Computing, http://www.emet.co.il/events/amd/processors.pdf Johnson D., „HP’s Mako processor”, Oct. 2001, ftp.parisc-linux.org/docs/whitepapers/mako_mpf_2001.pdf

  45. 10.6 PA-8900 (1) Models PA-8800(Mako) PA-8900(Shortfin) Dual/Quad-Core DC DC Achitecture PA-RISC 2.0 PA-RISC 2.0 Impl. of the cores Monolithic Monolithic Cores 2* PA-8700 2*PA-8700 Introduction 2/2004 5/2004 Technology 130 nm 130 nm Die size 366 mm2 366 mm2 Nr. of transistors 300 mtrs. 317 mtrs. fc [GHz] 0.8/1.0 1.1 L2 Size/allocation 32 MB/shared 64 MB/shared Implementation Tags on-chip, data off-chip Tags on-chip, data off-chip FSB 400 MT/s (16 B) 400 MT/s (16 B) Mem. Contr. Off-die Off-die TDP [W] 55 n.a. Table: Main features of HP’s PA-8800 and PA-8900 processors

  46. 10.6 Literature PA 8800/8900 MS, „HP PA-8800 RISCProcessor,” Lostcircuits, Oct. 2001, http://www.lostcircuits.com/cpu/hp_pa8800/2.shtml Johnson D., „HP’s Mako processor”, Oct. 2001, ftp.parisc-linux.org/docs/whitepapers/mako_mpf_2001.pdf Weissmann P., „The OpenPA Project,” First Edition, Berlin, 2007, http://www.openpa.net/openpa-print_1-0.pdf

  47. 10.7. RMI’ MC processors • XLR line (embedded)

  48. 10.7 RMI’s MC processors XLR line (embedded) 90 nm 5/2005 • XLR

  49. 10.7 XLR line (1) Aim: Embedded systems, such as processing cores from packet data transfers, cryptography functions, authentication operations, TCP/IP CRC calculations and network interface data management. Cores: 64-bit MIPS64 with XLR enhancements 4-way multithreaded up to 1.5 Gz 32KB L1 I$, 32 KB L1 D$ branch prediction Figure: XLR cores Source: http://www.razamicroelectronics.com/documents/XLR_PO_20050512_Product_Overview.pdf

  50. 10.7 XLR line (2) Figure: Architecture of the XLR family http://www.razamicroelectronics.com/documents/XLR_Family_2001PB_Product_Brief.pdf

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