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WELCOME TO EE457 COMPUTER SYSTEMS ORGANIZATION. THREE MAIN TOPICS 1. CPU DESIGN 2. MEMORY SYSTEM 3. COMPUTER ARITHMETIC. CPU DESIGN MICRO-ARCHITECTURE DESIGN GENERAL DIGITAL SYSTEM DESIGN. MEMORY SYSTEM DESIGN CACHE + VIRTUAL MEMORY.
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THREE MAIN TOPICS1. CPU DESIGN2. MEMORY SYSTEM3. COMPUTER ARITHMETIC
CPU DESIGNMICRO-ARCHITECTURE DESIGNGENERAL DIGITAL SYSTEM DESIGN
COMPUTER ARITHMETIC2’s Complement Arithmetic Review FAST ADDERSFAST MULTIPLIERSNON-LINEAR PIPELINESFOR ARTHMETIC OPERATIONS
COURSE PRE-REQUISITESEE201LINTRODUCTION TO DIGITAL CIRCUITSEE357BASIC ORGANIZATION OF COMPUTER SYSTEMS
LECTURES & DISCUSSIONSLECTURES:(a) 08:00-9:20AM MW MAP105(b) 04:00-5:20PM MW ZHS252 (c) 12:30-1:50PM TTh ZHS252 (d) 03:30-4:50PM TTh OHE122 DISCUSSIONS: (a) 01:00-01:50PM W OHE122(b) 09:00-09:50AM F KAP156 (c) 12:00-12:50PM F SLH102 (d) 03:00-03:50PM F SLH100 cancelled
EXAMINATIONS (Common to all 4 sections)(a) Quiz (~10%)Friday Sept. 27, 2013 10:00 AM - 12:30 PM PST (the quiz slot extended by 40 min).(b) Midterm (~20%)Friday Nov. 1, 2013 10:00 AM - 12:30 PM PST (the quiz slot extended by 40 min).(c) Final (~30%)Monday, Dec. 16, 2013 4:30-7:20 PM PST (Exception schedule, Time extended by 50 min)
No make up exams, sorry Then Exam conflict? OtherExam EE457Exam OtherExam EE457Exam OtherExam EE457Exam or
COURSE WEIGHTSQuiz ~10%MIDTERM EXAM ~20%HOMEWORKS 10 - 15%DESIGN PROJECTS 25 - 35%FINAL EXAM ~30%
LATE PENALTYHOMEWORKS:UP TO 5% PER DAYIF SOLUTION IS NOT DISTRIBUTED
LATE PENALTYLABS:2% PER DAY UP TO 7 DAYS 3% PER DAY AFTER 7 DAYS if specifically allowedThe last lab may not have this much flexibility.
LECTURE CLASS ATTENDANCEPENALTY FOR MISSING:1% FOR 5TH, 6TH AND 7TH2% FOR 8TH AND 9TH4% FOR 10TH AND AFTERPENALTY FOR MISSING DISCUSSION CLASS:HALF OF LECTURE CLASS MISSING PENALTY0.5% FOR 3rd, 4TH, 5TH, 6TH1% FOR 7TH AND AFTER
Two instructors:1. Gandhi Puvvada gandhi@usc.edu2. WaleedDweik dweik@usc.eduCommon TAs (3), Mentors (6), and Graders (6 HW + 6 Lab)Common blackboard (den.usc.edu)Common discussions, assignments, and exams
DESIGN PROJECTSPARTIALLY COMPLETE DESIGN FILES Core design Verilog file: ~50% complete Testbench and wave.do files:~80% to 100% completeTTL DATABOOK NOT NECESSARY
Esperan Verilog Reference Guide Is posted on the BB for personal use of USC faculty and students.-- please do not distribute, do not post it anywhere
IEEE Verilog standard ieee-1364-2001for USC library members only -- please do not distribute
HOMEWORK:INDIVIDUAL EFFORTLAB: (1) VERILOG CODING, SIMULATION AND DEBUGGING TEAM EFFORT (2) JUSTIFICATION, END-OF-LAB QUESTIONSINDIVIDUAL EFFORT
CLASS WEBPAGEDEN BLACKBOARDden.usc.eduhttps://www.uscden.net/webapps/login/LEC / DIS WEBCASTSASSIGNMENTSANNOUNCEMENTSOFFICE HOURSEMAIL
Verilog language andModelSim SimulatorINTRO. LECTUREs are posted
Buy these two items from the Bookstores(1)TEXTBOOKComputer Organization & Design - The Hardware and Software Interface 4th edition (Revised Printing)By D. A. Patterson (Berkeley) and J. L. Hennesy (Stanford) (2)CLASS NOTECHAPTER 1 ON THE BLACK-BOARD=========================================Lab Manual.pdf files will be posted progressively on the BB
Understand, No need to memorize, Learn to design. Demonstrate your understanding in the exam~40 to ~50 hours of office hours per week
Grades • Very easy to get an A grade
Grades • Very easy to get an A grade • Equally easy to get a F grade
Grades • Very easy to get an A grade • Equally easy to get a F grade
We appreciate your efforts • ~ 60% of the class gets an A grade No place for the lazy and uninterested • ~20% of the class fails or drops
There is no competition. Everyone can get an A grade.You need to aspire for it,and you need to work for it.You get what you worked for.No grace grade (No minimum grade).