Efficient On-line Interconnect BIST in FPGAs with Provable Detectability for Multiple Faults

1. Efficient On-line Interconnect BIST in FPGAs with ProvableDetectability for Multiple Faults Vishal Suthar and Shantanu Dutt Dept. of ECE University of Illinois at Chicago

2. Outline • On-Line BIST – Concepts • Previous Work in Interconnect BIST • New Interconnect BIST: I-BIST • Motivation • Types of faults • On-line issues • Global Testing • Detailed Testing • Simulation results • Conclusions

3. C T O C CUT TPG WUT ORA CUT WUT Pass / fail On-line Built-In Self-Testing in FPGAs • Two column left spare for ROTE; one for • fault reconfiguration • ROTE roves across the FPGA • In each session diff. PLBs act as CUTs, • TPG and ORA. ROTE (ROving TEster) BISTer: TPG - Test Pattern Generator ORA - Output Response Analyser CUT - Cells Under Test T C C O SPARECOLUMN SPARECOLUMN WUT - Wires Under Test CIRCUIT CIRCUIT CIRCUIT WUT WUT

4. Interconnect BIST-- Motivation • Interconnects occupy ~ 90% of FPGA area • Multiple faults can easily occur for current and emerging nano-meter FPGAs; no current work detects all multiple faults • Many PLB BIST work, but much fewer on interconnect BIST

5. many Interconnect BIST– Past Work • Only few on-line interconnect BIST methods • # configurations high for previous on-line interconnect BIST: 10 for [Liu et al., CICC’01] • # of test vectors high for all previoys interconnect BIST • No prev. method has guarantd. 100% fault detectability for multiple faults • Fault diagnosability (% of faults correctly located) low for past methods • Our interconnect BIST method I-BIST will address and improve on all these issues

6. I-BIST – Objectives & Flow • Objectives: • To maximize diagnosability, even in presence of multiple faults, by avoiding • fault masking scenarios. • To reduce test time. • Dominant component of test time = configuration time • Hence minimize # configurations. • Secondary objective: minimize # test vectors. Approach: 1. First isolate the possible fault locations to a small set of interconnects in very few configurations -> Suspect Set, 2. Then diagnose interconnects of suspect set for faults. -- Global testing -- Detailed testing

7. I-BIST – Interconnect Faults • Testing wire-segments and switches • Faults considered: wire-segment -> stuck-at, stuck-open and bridged fault • switches -> stuck-open and stuck-closed.

8. Roving Tester Positions for I-BIST • Typical FPGA contains single-length, double-length and long wires. • whereas, a ROTE can occupy only two to three columns. • Hence, two types of ROTE are required: V-ROTE and H-ROTE

9. I-BIST – Tested Interconnects V-Set: Interconnects tested under V-ROTE • Uncovered switches are covered in the next ROTE position or in the H-ROTE

10. Test vector 1: 1 0 1 0 Test vector 2: 0 1 0 1 I-BIST – Global Testing: Idea • Multiple nets are formed • Multiple ORAs each comparing adj. nets • ORAs configured for 2-input XOR function • Pass complementary vectors on each adj. • net • => 2 test vectors {0101..} & {1010…}

11. Test vector 1: 1 0 1 0 Test vector 2: 0 1 0 1 n n n n 4 2 1 3 X X 0 1 0 TPG 0 0 1 ORA 1 w 1 ORA 2 Fail bridge w 2 ORA 3 I-BIST – Global Testing: Idea • Consider ORA(n2, n3) • Under fault-free conditions • ORA (2-ip XOR) output = 1 1 • Wire stuck-at fault @ n2 • ORA output = 0 1 (n2 stuck-at-0) • = 1 0 (n2 stuck-at-1) • Multiple stuck-at fault on n2 is going • to result in one type dominating at • the ORA input • Wires bridge fault • ORA output = 0 0

12. Test vector 0: 0 0 0 0 Test vector 1: 1 0 1 0 Test vector 2: 0 1 0 1 n n n n 4 2 1 3 1 0 0 1 0 TPG 0 0 1 ORA 1 w 1 ORA s-a-1 2 s-a-0 Fail w 2 ORA 3 I-BIST – Global Testing: Idea • Under fault-free conditions • ORA (2-ip XOR) output = 1 1 • Exception: one of the adjacent wire is • s-a-0 and other is s-a-1. • output = 1 1 = fault-free output • one more test vector required {0000…} or {111…} • Unexpected-comparison based test vectors • Fault-free output = 0 1 1 • Faulty output = 1 1 1

13. Test vector 0: 0 0 0 0 Test vector 1: 1 0 1 0 Test vector 2: 0 1 0 1 n n n n 4 2 1 3 0 1 0 TPG 0 0 1 ORA 1 w 1 ORA 2 Stuck-open Fail pass w 2 ORA 3 I-BIST – Global Testing: Idea Stuck-open fault: • Assunption: Stuck-open fault essentially • results in a s-a-0 fault in the affected part • Only detected if present between TPG • and ORA • A second stage of global testing reqd. • Switch stuck-open faults that are part • of the nets are similarly detected • All switches are included in some net • across 5 configurations of net patterns

14. I-BIST – Global Testing: Idea (contd) n n n n n n n n 4 4 2 2 1 1 3 3 w w 1 1 w w 2 2 Stuck-open fault (contd): Two stages of global testing phase needed – can be done simultaneously 0 0 1 0 1 0 TPG 0 0 0 0 1 1 ORA ORA 1 1 ORA ORA 2 2 Stuck-open Stuck-open Fail Fail ORA ORA 3 3 TPG

15. n n n n 4 2 1 3 0 1 0 TPG 0 0 1 ORA 1 w 1 ORA Stuck-closed 2 w 2 ORA 3 I-BIST – Global Testing: Idea (contd) Switch stuck-closed fault: • Unlike other faults, switch stuck-closed • fault cannot be detected by including the • switch on a net

16. I-BIST – Global Testing: Idea (contd) Switch stuck-closed fault (contd): • Unlike other faults, switch stuck-closed • fault cannot be detected by including the • switch on a net • Form nets in such a way that a • switch stuck-closed fault bridges the • two nets. • We refer to such switches as • Spanning switches

17. I-BIST – Global Testing: Properties Theorem:Any number of faults in each net tested will be detected by the multiple ORA technique of global testing. Furthermore, a stuck-closed fault in any spanning switch between every pair of nets compared by an ORA will also be detected. Corollary:Fault masking cannot occur in global testing, even in presence of faults of the same type.

18. Global Testing Dual-type multiple ORA technique • multiple nets formed • similarly configured nets – • net-set e.g. net-sets n & l

19. Global Testing Dual-type multiple ORA technique • Two types of ORA comparison: • 1. Intra-net-set comparison • Adjacent nets of same net-set • compared • E.g., • target: all faults other than switch • stuck-closed fault • Inter-net-set comparison • Nets i of the two net-sets compared • E.g. • target: switch stuck-closed faults • in spanning switches

20. Global Testing – Five Configurations Theorem:Any # of fault(s) in the V-set (interconnects tested in V-ROTE) will be detected by the 5 configurations of the global testing phase.

21. Suspect interconnect Fault-free interconnect Detailed Testing • Diagnose faults on faulty nets of global testing phase. • Simple approach: Flat intersection • Suspect set = interconnects of failed nets found in global testing phase • Each interconnect element of suspect set compared with fault-free components. Drawback: Suspect set may be too large, even in presence of few fault.

22. Detailed testing – Divide & Conquer (D&C) Better approach: Divide & Conquer ( D & C) O O • Failed nets divided into 2 sub-nets • Failed configurations re-applied independently on both sets of sub-nets. • Only the comparisons that failed in global testing phase are reqd. • Switches between the two sub-nets tested using same configurations minimized to two rows A O

23. Detailed Testing – D&C (contd): Global testing Detailed testing O O O Switch stuck-closed O A O

24. Simulation Setup • Simulated a 32 x 32 FPGA with single-length segments in C • Fault injector injects faults in wire segments and switches randomly at the specified fault probability (density/100)

25. Simulation Setup and Fault Latency Results • Simulated a 32 x 32 FPGA with single-length segments in C • Fault injector injects faults in wire segments and switches randomly at the specified fault probability (density/100) Fault latency ( # configurations) vs. Fault density

26. Analytical Results & Comparison to Prev Work many Overall Fault Diagnosability Results Fault coverage (diagnosability) versus fault density

27. Conclusions • Presented a new interconnect BIST technique I-BIST for FPGAs—uses a hierarchical, adaptive approach, unexpected-comparison based test vectors • Applicable to both on-line and off-line BIST • I-BIST has 100% guaranteed fault detectability in the presence of multiple faults – a first • I-BIST has ~ 100% fault diagnosability (empirically) • I-BIST has the fewest configurations—5—per WUT-set in global testing • I-BIST has the fewest # of test vectors—3—per WUT-set testing phase • I-BIST uses an adaptive D&C phase in detailed testing to home in to the offending faults quickly • New work: Combined PLB and interconnect BIST w/o fault-free assumptions about any components—to appear at VTS’06