Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free Assumptions

1. Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free Assumptions Vishal Suthar and Shantanu Dutt Electrical and Computer Engineering University of Illinois at Chicago.

2. Outline • The problem of fault-free assumptions & other stories • Iterative Bootstrapping (IB) – A general solution • Mixed BIST: Combining PLB & interconnect testing with IB—no fault-free assumptions • Recent work in PLB BIST (HD-BIST) • Recent work in interconnect BIST (I-BIST) • Simulation Results • Conclusions

3. CUT TPG WUT ORA CUT WUT Pass / fail Built-In Self-Test in FPGAs—Basic Concepts Comparison based BIST: TPG - Test Pattern Generator ORA - Output Response Analyser CUT - Cells Under Test • In each session diff. PLBs act as CUTs, • TPG and ORA. WUT - Wires Under Test WUT Gross syndrome (GS): The gross syndromeof a session is the overall fail/pass (X/√ ) result of a session. Match in all CUT outputs => ORA output = 0 => GS = pass (√ ) Else ORA output = 1 => GS = fail (X) WUT

4. BISTer-1: D A A D A D A D CUT CUT CUT TPG TPG ORA ORA CUT CUT ORA TPG ORA CUT TPG CUT CUT B B C C C B B C (S1) (S2) (S3) (S4) BISTer-1 BISTer-0 100 90 80 Fault coverage (%) 70 60 50 40 30 8.8 (1) 16.9 (2) 26.6 (3) Fault density (cluster density) (%) (a) Random faults (b) Clustered faults Drawbacks in deterministic BIST techniques (V. Verma, S. Dutt, V. Suthar, DAC 2004) Theorem:BISTer-1 is 1/4 diagnosable

5. Fallacy of Fault-Free Assumptions • Limited / Incorrect diagnosability in presence of multiple faults • in the BISTer area. • Unrealistic assumptions: a) The test circuit (TPG & ORA) is fault-free. • b) No fault masking; c) no more than 1-2 faults in BISTer area BISTer CUT GS= pass (non-det.) ORA TPG GS= fail (false +ve) CUT 2. Absence of BIST techniques that can diagnose faults present in PLBs as well as interconnects. Unrealistic assumption: while testing PLBs the interconnects used in the BISTer area are fault-free and similarly, while testing interconnects the PLBs forming the test circuit are fault-free.

6. Iterative Bootstrapping (IB) Test circuit with f-free prob. = Use redundancy (e.g. TMR) to increase Test PLBs conf. for ORA and TPG functions & reqd. interconnects using o/p = Test circuit with f-free prob. Test circuit No Yes Final test circuit Need: An ability to detect and diagnose faults in presence of multiple faults and/or clustered fault patterns in both PLBs and interconnects, with high probability. Solution: Iterative bootstrapping for obtaining fault-free test circuits (w/ fault-free PLBs & interconnects)

7. Iterative Bootstrapping (IB) Yes Yes • Consider TMR as the redundant circuit: p = prob. of a faulty PLB, • q1 (q2) = prob of fault-free TMR TPG/ORA (1 PLB impl.) in 1st (2nd) iter of IB • Theorem: If prob. of correct oper. f(q) [q=fault-free prob. of component] is monotonically non-decreasing, and f(q0=1-p) >= 1-p, then IB provides us w/ s sequence of redundant test circuits with monotonically non-decreasing fault-free probabilities q1, q2, ….., qk. • Does it always work? • If not, are there conditions under which it works? • Are these conditions realistic? No

8. requires F-free interconnect PLB testing obtained from obtained from requires F-free TPGs/ORAs Interconnect testing Mixed PLB and Interconnect BIST • Two high-diagnosability BIST techniques used. • HD-BIST (High-Diagnosability BIST) – PLB testing [GLSVLSI’05] • I-BIST (Interconnect BIST) – Interconnect testing [DATE’06] • Reqmt for reliable mixed testing w/ faults in PLBs & interconnects: • A classic chicken-&-egg problem (which comes first). • Solution: Break the cycle via Iterative Bootstrapping

9. First phase – IB w/ TMR test ckt. rqd. for phase Non TMR’ed Phase test ckt. rqd. for phase Mixed PLB and Interconnect BIST (contd) • Solution: Break the cycle via IB and then interleave the various stages of HD-BIST and I-BIST so that fault-free components (w/ high prob.) are available to test the next stage. Our approach: Fault state unknown

10. Tester Stick TPG ORA TPG D E F CUT TPG CUT A B C Testee Stick Theorem: = prob. of shuffled TPG skipping a test vector. = prob. of normal TPG skipping a test vector. TPG ORA TPG TPG ORA TPG D E F D E F p = prob. of a PLB being faulty. TPG CUT CUT CUT CUT TPG C A B C A B Mixed-BIST: PLB BIST Stages HD-BIST [Suthar & Dutt, GLSVLSI’05] START Bootstrapping phases (2) o/p = fault-free ORA / stick (if exists) Global testing – Fault detection & gross diagnosis phase TPG shuffling scheme (instead of TMR) to reduce test vector skipping probability o/p = suspect PLBs & fault-free sticks Detailed testing: Adaptive diagnosis phase o/p = faulty PLBs END

11. Random faults Clustered faults ) ) HD_3 % % 100 100 ( ( HD_1 HD_3/1 e e 90 90 BISTer-1 g g a a 80 80 r r BISTer-1 e e 70 70 v v STAR 60 o o 60 c c 50 t t STAR l l 50 40 u u a a 30 40 F F 8.8 16.9 26.6 1 2 5 7 10 15 20 25 (1.0) (2.0) (3.0) Fault density (%) Cluster density (%) HD-BIST Experimental Results • HD-BISTer is compared with previous best online BIST techniques: • STAR BISTer proposed by [M. Abramovici et. al., ITC’00] and BISTer-1 • HD_3 -> HD-BISTer with TPG shuffling • HD_1 -> HD-BISTer without TPG shuffling. FAULT COVERAGE:

12. Mixed-BIST: Interconnect BIST Stages Global Testing (1/5 configs) I-BIST [Suthar & Dutt, DATE’06] • Approach: • 1. Global Testing: First isolate the possible fault locations to a small set of interconnects in very few configurations -> Suspect Set • Detailed Testing: Then diagnose interconnects of suspect set for faults using divide-&-conquer and in the final iteration by comparison to known fault-free interconnects

13. Fault coverage (diagnosability) versus fault density I-BIST: Results • Theoretical Results: • Theorem: I-BIST has 100% guaranteed fault detectability in the presence of multiple faults – a first • I-BIST has the fewest configurations—5—per WUT-set in global testing • I-BIST has the fewest # of test vectors—3—per WUT-set testing phase Empirical Results:

14. First phase – IB w/ TMR Test ckt. rqd. for phase Non TMR’ed Phase Test ckt. rqd. for phase Mixed-BIST– Summary of Techniques • Our Mixed-BIST (M-BIST) approach attempts to significantly reduce these negative effects via • a careful application of iterative bootstrapping • interleaving of various stages of I-BIST and HD-BIST

15. Mixed BIST: Combining & Interleaving IB, I-BIST & HD-BIST

16. Simulation Results – Fault Coverage • Comparison of PLB and interconnect testing in • M-BIST (without fault-free assumptions) v/s • HD-BIST (with fault-free assumptions) & • I-BIST (with fault-free assumptions) Fault coverage – random faults M-BIST v/s HD-BIST(w/ f-free assumptions) M-BIST v/s I-BIST(w/ f-free assumptions) 1.5 % difference 2 % difference

17. Simulation Results – False Positives False positives – fault-free components incorrectly diagnosed as faulty. -- measured as a percentage of faults inserted. False positive results – random faults M-BIST v/s HD-BIST(w/ f-free assumptions) M-BIST v/s I-BIST(w/ f-free assumptions) 200% 40% 5 % 0%

18. Conclusions • Goal: Mixed PLB and Interconnect BIST that does not require any fault-free assumptions in order to: • improve diagnosability and reduce false positives • in the presence of clustered and high density faults in both PLBs and interconnects • Introduced the novel concept of general iterativebootstrapping for this purpose that can be used in different test and fault tolerance domains • Analyzed the mathematical conditions for improved diagnosis using iterative bootstrapping • Applied iterative bootstrapping in novel ways (TMR, shuffled TPGs, TPGs w/o i/o faults) to develop a Mixed BISTer M-BIST sans fault-free assumptions • Achieved our aim of accurate PLB and interconnect diagnosis • Future Work: Built-in controller for diagnosis and reconfiguration

19. THANK YOU

20. C T O C CUT TPG WUT ORA CUT WUT Pass / fail Built-In Self-Test in FPGAs—On-Line & Off-Line • Two column left spare for ROTE; one for • fault reconfiguration • ROTE roves across the FPGA • In each session diff. PLBs act as CUTs, • TPG and ORA. ROTE (ROving TEster) BISTer: TPG - Test Pattern Generator ORA - Output Response Analyser CUT - Cells Under Test T C C O SPARECOLUMN SPARECOLUMN WUT - Wires Under Test CIRCUIT CIRCUIT CIRCUIT WUT WUT

21. Suspect interconnect Fault-free interconnect Mixed-BIST: Interconnect BIST Stages (contd) Global testing Detailed testing—Divide-&-Conquer O O O Switch stuck-closed O A O

22. M-BISTer (Mixed-BISTer):