a Università degli Studi di Pavia b Università degli Studi di Bergamo c INFN Pavia

1. Analog front-ends for monolithic and hybrid pixels developed with a 3D CMOS process S.Zuccaa,c, L. Gaionib,c, A. Manazzaa,c, M. Manghisonib,c, L. Rattia,c V. Reb,c, E. Quartieria,c, G. Traversib,c aUniversità degli Studi di Pavia bUniversità degli Studi di Bergamo cINFN Pavia dUniversità degli Studi di Pisa eINFN Pisa 8th International Meeting on Front-End Electronics FEE 2011 Bergamo, 23-27 May 2011

2. Outline SuperB experiment and SVT Layer0 requirements Vertical Integration (3D) CMOS Technologies Why are they so attractive for HEP applications? DNW MAPS and hybrid pixels in 3D technology Analog FE for Apsel VI 3D MAPS chip General description Issue for large matrices: voltage drop on analog VDD/GND lines. 3D Analog FE for Superpix1 hybrid pixels chip Comparison with the Apsel VI analog FE Fine tuning system for the threshold correction Conclusion and future plans

3. SuperB factory The SuperB factory, an high luminosity e+-e- collider intended for HEP experiments, has been recently funded by the Italian Ministry for Education, University and Research. Silicon Vertex Tracker very similar to that of the 5 layer BaBar experiment, completed by a Layer0 very close to the IP (about 1.5 cm) to improve the vertex resolution. Other requirements: Low material budget (<1% X0) Fine granularity (50 μm pitch) Two possible approaches for the SuperB Layer0 at full luminosity: CMOS MAPS:can provide low material budget and small pitch. Hybrid Pixels:more mature technology, with somewhat worse material budget features.

4. Vertical Integration (3D) CMOS Technologies In wafer level 3D processes, multiple layers of planar devices are stacked and interconnected using inter-layer connections. Advantages for HEP particle pixel detectors: The analog section (and the sensor) do not share the same substrate with the noisy digital readout. Less material in the IP: monolithic structure of the final chip enables post-process thinning. Dead area reduction: the readout electronics can be designed with virtually no peripheral circuits. Apsel VI and Superpix1 have been designed in the Globalfoundries-Tezzaron 130 nm 3D CMOS process. Higher functional density more complex pixel readout chain (i.e. sparsified, triggered readout techniques).

5. DNW MAPS and hybrid pixels in 3D Technologies DNW MAPS Hybrid pixels Digital section Digital section 1st Layer 2nd Layer Analog section DNW sensor Analog section sensor Back to back assembled devices from two chips, by means of bump bonding techniques. They feature: The inversely biased DNW acts as a collecting electrode. A readout chain is used for Q-V conversion gain decoupled from CD high SNR 100% fill factor no crosstalk between the digital readout electronics and the sensor NMOS analog FE devices are built-in in the deep N-well. Large material budget innovative direct bonding techniques (Zyptronix or TMicro/ZyCube) PMOS can be included in the design and placed in a separate layer charge collection efficiency close to 100%. In 3D design the use of two layers provides a lot of functionality in the pixel cell.

6. In-pixel logic for a time-ordered readout Complex in-pixel logic can be implemented without reducing the pixel collection efficiency (thanks to 3D integration) even improving the readout performance (readout could be data push or triggered). Timestamp (TS) is broadcast to pixels and each pixel latches the current TS when fires. • Matrix readout is TS ordered • A readout TS enters the pixel and an HIT-OR-OUT is generated for columns with hits associated to that TS • A column is read only if HIT-OR-OUT=1 • DATA_OUT is generated for pixels in the active columns with hits associated to that TS. Courtesy of F. Morsani (INFN PI)

7. Apsel VI front-end architecture TIER2 (top) TIER1 (bottom) First stage: charge PA with a CFB countinously discharged by an NMOS biased in deep subthreshold region. Second stage: RC-CR shaper with a transconductor feedback network: Vbl chip wide distributed by an external voltage reference (not affected by voltage drop issues) Voltage drop effects reduction on the channel-to-channel dispersion of the DC voltage at the shaper output (Vbl) Third stage: comparator (placed on the top tier along with the in-pixel readout logic).

8. Charge Preamplifier Two local feedback networks (M4,M5 and M6,M7) to increase the small signal resistance at the node C. Cp value is a trade-off between noise and bandwidth. MFB is used to discharge CFB after the particle hit. DC gain=84 dB C F-3dB= 40 kHz

9. Shaping stage The transconductor keeps the circuit in the correct bias point and set the output waveform peaking time at the designed value. Cascode input stage and output source follower. First order RC-CR shaping stage: tp: peaking time It can be demonstrated that, in order to obtain an output waveform with the desired tp (constant at the varying of the input signal amplitude), the following equations must be satisfied: A0: open loop DC gain f0: -3dB cutoff frequency

10. Shaping stage Since C2 value has to be small (≈ 50 fF) for area occupancy reasons, Gm value must be very low (≈ 20 nS) to obtain the desired tp (≈ 300 ns) Itransc ≈ 10-9 A Standard solution Source degeneration solution Mirrored load transconductor with source degeneration resistance. Mirrored load transconductor: Higher Itransc Wider linear range

11. Voltage drop on analog VDD/GND lines May be an issue with large matrices of relatively current-hungry detectors AVDDpixel AVDDperipheral Apsel VI features: Ianalog_cell=25 μA 128x100 pixels matrix for the next run I=120 nA Considering the case of a larger matrix (i.e. 256x256 elements), supplied from both sides, we obtain the following voltage drop on AVDD and AGND: Itransc≈ 2.5 nA Isib≈120 nA AGNDperipheral AGNDpixel DVd=15/20 mV (typ/max) M. Manghisoni, E. Quartieri et al.,“High Accuracy Injection Circuit for Pixel-Level Calibration of Readout Electronics” presented at the 2010 IEEE Nuclear Science Symposium Conference, Knoxville, USA, October 30 - November 6 2010. Voltage drop on the AVDD and AGND lines causes changes in some pixel current sources, in particular in the shaper input branch and in the transconductor. These current changes lead to a degradation of the front-end performance (i.e. charge sensitivity and peaking time).

12. Effects on the shaper output waveform Voltage drop is simulated as a symmetrical voltage variation in the analog power (AVDD) and ground (AGND) lines. AVDD=1.5 V-ΔVd, AGND=ΔVd ΔVD=0 mV ΔVD=60 mV ΔVD=20 mV ΔVD=40 mV ΔVD=40 mV ΔVD=20 mV ΔVD=60 mV ΔVD=0 mV w/o voltage drop compensation with voltage drop compensation

13. Effects on peaking time and charge sensitivity Voltage drop is simulated as a symmetrical voltage variation in the analog power (AVDD) and ground (AGND) lines. AVDD=1.5 V-ΔVd, AGND=ΔVd Charge sensitivity variation [%] Peaking time variation [ns]

14. Apsel VI performance

15. Superpix1 3D hybrid chip front-end architecture TIER1 (bottom) TIER2 (top) C2 linearly discharged by a constant current Imir linear increase of the recovery time with input signal amplitude. Fine tuning system in order to reduce the threshold dispersion: Lower detector parasitic capacitance (CD≈150 fF): lower noise and power consumption IDAC is set by a 4 bit current steering DAC in each channel. Lower power consumption (Icell≈ 7μA) reduces the voltage drop effects on the channel-to-channel baseline voltage (Vbl) dispersion current mirror, also less noisy than transconductor. All in a 50 μm pixel pitch DAC driven by a thermometric code decoder.

16. Superpix1 analog front-end Main features This plot shows that an optimum condition exists for the threshold correction operation (DAC output range ≈5σth):

17. Conclusion and future plans Two different approaches are being considered for the design of the readout chip in view of applications to the SVT Layer0 of the SuberB factory. Apsel VI and Superpix1 will be fabricated in the Globalfoundries-Tezzaron 130 nm 3D CMOS technology (to be submitted Q4 2011). MAPS and hybrid pixels can capitalize on 3D CMOS processes in terms of: higher collection efficiency (MAPS) immunity of the analog section (and of the sensor in MAPS) from digital signals increase of the functional density in the pixel cell Future steps include the characterization of both the chips (2011-12).