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EELE 367 – Logic Design

EELE 367 – Logic Design. Module 4 – Combinational Logic Design with VHDL Agenda Decoders/Encoders Multiplexers/ Demultiplexers Tri-State Buffers Comparators Adders (Ripple Carry, Carry-Look-Ahead) Subtraction Multiplication Division (brief overview). Integrated Circuit Scaling.

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EELE 367 – Logic Design

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  1. EELE 367 – Logic Design • Module 4 – Combinational Logic Design with VHDL • Agenda • Decoders/Encoders • Multiplexers/Demultiplexers • Tri-State Buffers • Comparators • Adders (Ripple Carry, Carry-Look-Ahead) • Subtraction • Multiplication • Division (brief overview)

  2. Integrated Circuit Scaling • Integrated Circuit ScalesExample# of TransistorsSSI - Small Scale Integrated Circuits Individual Gates 10's MSI - Medium Scale Integrated Circuits Mux, Decoder 100'sLSI - Large Scale Integrated Circuits RAM, ALU's 1k - 10kVLSI - Very Large Scale Integrated Circuits uP, uCNT 100k - 1MULSI - Ultra Large Scale Integrated Circuits Modern uP's > 1MSoC - System on Chip Microcomputers SoP - System on Package Different technology blending- we use the terms SSI and MSI. Everything larger is typically just called "VLSI"- VLSI covers design that can't be done using schematics or by hand.

  3. Decoders • Decoders- a decoder has n inputs and 2n outputs- one and only one output is asserted for a given input combinationex) truth table of decoderInput Output 00 0001 01 0010 10 0100 11 1000- these are key circuits for a Address Decoders

  4. Decoder • Decoder Structure- The output stage of a decoder can be constructed using AND gates- Inverters are needed to give the appropriate code to each AND gate- Using AND/INV structure, we need: 2n AND gates n Inverters Showing more inverters than necessary to illustrate concept

  5. Decoders • Decoders with ENABLES- An Enable line can be fed into the AND gate- The AND gate now needs (n+1) inputs- Using positive logic: EN = 0, Output = 0 EN =1, Output depends on input code

  6. Decoders • Decoder Example - Let's design a 2-to-4 Decoder using Structural VHDL- We know we need to describe the following structure:- We know what we'll need: 2n AND gates = 4 AND gates n Inverters = 2 Inverters Showing more inverters than necessary to illustrate concept

  7. Decoder • Decoder Example- Let's design the inverter using concurrent signal assignments….entity inv is port (In1 : in STD_LOGIC; Out1 : out STD_LOGIC); end entity inv;architecture inv_arch of inv is begin Out1 <= not In1; end architecture inv_arch;

  8. Decoders • Decoder Example- Let's design the AND gate using concurrent signal assignments….entity and2 is port (In1,In2 : in STD_LOGIC; Out1 : out STD_LOGIC); end entity and2;architecture and2_arch of and2 is begin Out1 <= In1 and In2; end architecture and2_arch;

  9. Decoders • Decoder Example- Now let's work on the top level design entity called "decoder_2to4"entity decoder_2to4 is port (A,B : in STD_LOGIC; Y0,Y1,Y2,Y3 : out STD_LOGIC); end entity decoder_2to4;

  10. Decoders • Decoder Example- Now let's work on the top level design architecture called "decoder_2to4_arch"architecture decoder_2to4 _arch of decoder_2to4 is signal A_n, B_n : STD_LOGIC; component inv port (In1 : in STD_LOGIC; Out1 : out STD_LOGIC); end component; component and2 port (In1,In2 : in STD_LOGIC; Out1 : out STD_LOGIC); end component; begin ………

  11. Decoders • Decoder Example- cont…. begin U1 : inv port map (A, A_n); U2 : inv port map (B, B_n); U3 : and2 port map (A_n, B_n, Y0); U4 : and2 port map (A, B_n, Y1); U5 : and2 port map (A_n, B, Y2); U6 : and2 port map (A, B, Y3);end architecture decoder_2to4 _arch;

  12. Encoders • Encoder- an encoder has 2n inputs and n outputs- it assumes that one and only one input will be asserted- depending on which input is asserted, an output code will be generated- this is the exact opposite of a decoder ex) truth table of binary encoderInput Output 0001 00 0010 01 0100 10 1000 11

  13. Encoders • Encoder- an encoder output is a simple OR structure that looks at the incoming signals ex) 4-to-2 encoderI3 I2 I1 I0Y1 Y0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 0 1 0 0 0 1 1 Y1 = I3 + I2 Y0 = I3 + I1

  14. Encoders • Encoders in VHDL- 8-to-3 binary encoder modeled with Structural VHDL entity encoder_8to3_binary is generic (t_delay : time := 1.0 ns); port (I : in STD_LOGIC_VECTOR (7 downto 0); Y : out STD_LOGIC_VECTOR (2 downto 0) ); end entity encoder_8to3_binary; architecture encoder_8to3_binary_arch of encoder_8to3_binary is component or4 port (In1,In2,In3,In4: in STD_LOGIC; Out1: out STD_LOGIC); end component; begin U1 : or4 port map (In1 => I(1), In2 => I(3), In3 => I(5), In4 => I(7), Out1 => Y(0) ); U2 : or4 port map (In1 => I(2), In2 => I(3), In3 => I(6), In4 => I(7), Out1 => Y(1) ); U3 : or4 port map (In1 => I(4), In2 => I(5), In3 => I(6), In4 => I(7), Out1 => Y(2) ); end architecture encoder_8to3_binary_arch;

  15. Encoders entity encoder_8to3_binary is generic (t_delay : time := 1.0 ns); port (I : in STD_LOGIC_VECTOR (7 downto 0); Y : out STD_LOGIC_VECTOR (2 downto 0) ); end entity encoder_8to3_binary; architecture encoder_8to3_binary_arch of encoder_8to3_binary is begin ENCODE : process (I) begin case (I) is when "00000001" => Y <= "000"; when "00000010" => Y <= "001"; when "00000100" => Y <= "010"; when "00001000" => Y <= "011"; when "00010000" => Y <= "100"; when "00100000" => Y <= "101"; when "01000000" => Y <= "110"; when "10000000" => Y <= "111"; when others => Y <= "ZZZ"; end case; end process ENCODE; end architecture encoder_8to3_binary_arch; • Encoders in VHDL- 8-to-3 binary encoder modeled with Behavioral VHDL

  16. Priority Encoders • Priority Encoder- a generic encoder does not know what to do when multiple input bits are asserted- to handle this case, we need to include prioritization- we decide the list of priority (usually MSB to LSB) where the truth table can be written as follows:ex) 4-to-2 encoder I3 I2 I1 I0Y1 Y0 1 x xx 1 1 0 1 x x 1 0 0 0 1 x 0 1 0 0 0 1 0 0 - we can then write expressions for an intermediate stage of priority bits “H” (i.e., Highest Priority): H3 = I3 H2 = I2∙I3’ H1 = I1∙I2’∙I3’ H0 = I0∙I1’∙I2’∙I3’ - the final output stage then becomes: Y1 = H3 + H2 Y0 = H3 + H1

  17. Priority Encoders • Priority Encoders in VHDL- 8-to-3 binary priority encoder modeled with Behavioral VHDL- If/Then/Else statements give priority- Concurrent Conditional Signal Assignments give priority entity encoder_8to3_priority is generic (t_delay : time := 1.0 ns); port (I : in STD_LOGIC_VECTOR (7 downto 0); Y : out STD_LOGIC_VECTOR (2 downto 0) ); end entity encoder_8to3_priority; architecture encoder_8to3_priority_arch of encoder_8to3_priority is begin Y <= "111" when I(7) = '1' else -- highest priority code "110" when I(6) = '1' else "101" when I(5) = '1' else "100" when I(4) = '1' else "011" when I(3) = '1' else "010" when I(2) = '1' else "001" when I(1) = '1' else "000" when I(0) = '1' else -- lowest priority code "ZZZ"; end architecture encoder_8to3_priority_arch;

  18. Multiplexer • Multiplexer- gates are combinational logic which generate an output depending on the current inputs- what if we wanted to create a “Digital Switch” to pass along the input signal?- this type of circuit is called a “Multiplexer”ex) truth table of MultiplexerSelOut 0 A 1 B

  19. Multiplexer • Multiplexer- we can use the behavior of an AND gate to build this circuit: X∙0 = 0 “Block Signal”X∙1 = X “Pass Signal”- we can then use the behavior of an OR gate at the output state (since a 0 input has no effect) to combine the signals into one output

  20. Multiplexer • Multiplexer- the outputs will track the selected input- this is in effect, a “Switch”ex) truth table of MultiplexerSelA BOut 0 0 x 0 0 1 x 1 1 x 0 0 1 x 1 1 - an ENABLE line can also be fed into each AND gate

  21. Multiplexer • Multiplexers in VHDL- Structural Model entity mux_4to1 is port (D : in STD_LOGIC_VECTOR (3 downto 0); Sel : in STD_LOGIC_VECTOR (1 downto 0); Y : out STD_LOGIC); end entity mux_4to1; architecture mux_4to1_arch of mux_4to1 is signal Sel_n : STD_LOGIC_VECTOR (1 downto 0); signal U3_out, U4_out, U5_out, U6_out : STD_LOGIC; component inv1 port (In1: in STD_LOGIC; Out1: out STD_LOGIC); end component; component and3 port (In1,In2,In3 : in STD_LOGIC; Out1: out STD_LOGIC); end component; component or4 port (In1,In2,In3,In4: in STD_LOGIC; Out1: out STD_LOGIC); end component; begin U1 : inv1 port map (In1 => Sel(0), Out1 => Sel_n(0)); U2 : inv1 port map (In1 => Sel(1), Out1 => Sel_n(1)); U3 : and3 port map (In1 => D(0), In2 => Sel_n(1), In3 => Sel_n(0), Out1 => U3_out); U4 : and3 port map (In1 => D(1), In2 => Sel_n(1), In3 => Sel(0), Out1 => U4_out); U5 : and3 port map (In1 => D(2), In2 => Sel(1), In3 => Sel_n(0), Out1 => U5_out); U6 : and3 port map (In1 => D(3), In2 => Sel(1), In3 => Sel(0), Out1 => U6_out); U7 : or4 port map (In1 => U3_out, In2 => U4_out, In3 => U5_out, In4 => U6_out, Out1 => Y); end architecture mux_4to1_arch;

  22. Multiplexer • Multiplexers in VHDL- Structural Model w/ EN entity mux_4to1 is port (D : in STD_LOGIC_VECTOR (3 downto 0); Sel: in STD_LOGIC_VECTOR (1 downto 0); EN : in STD_LOGIC; Y : out STD_LOGIC); end entity mux_4to1; architecture mux_4to1_arch of mux_4to1 is signal Sel_n : STD_LOGIC_VECTOR (1 downto 0); signal U3_out, U4_out, U5_out, U6_out : STD_LOGIC; component inv1 port (In1: in STD_LOGIC; Out1: out STD_LOGIC); end component; component and4 port (In1,In2,In3,In4: in STD_LOGIC; Out1: out STD_LOGIC); end component; component or4 port (In1,In2,In3,In4: in STD_LOGIC; Out1: out STD_LOGIC); end component; begin U1 : inv1 port map (In1 => Sel(0), Out1 => Sel_n(0)); U2 : inv1 port map (In1 => Sel(1), Out1 => Sel_n(1)); U3 : and4 port map (In1 => D(0), In2 => Sel_n(1), In3 => Sel_n(0), In4 => EN, Out1 => U3_out); U4 : and4 port map (In1 => D(1), In2 => Sel_n(1), In3 => Sel(0), In4 => EN, Out1 => U4_out); U5 : and4 port map (In1 => D(2), In2 => Sel(1), In3 => Sel_n(0), In4 => EN, Out1 => U5_out); U6 : and4 port map (In1 => D(3), In2 => Sel(1), In3 => Sel(0), In4 => EN, Out1 => U6_out); U7 : or4 port map (In1 => U3_out, In2 => U4_out, In3 => U5_out, In4 => U6_out, Out1 => Y); end architecture mux_4to1_arch;

  23. Multiplexer entity mux_4to1 is port (D : in STD_LOGIC_VECTOR (3 downto 0); Sel : in STD_LOGIC_VECTOR (1 downto 0); EN : in STD_LOGIC; Y : out STD_LOGIC); end entity mux_4to1; architecture mux_4to1_arch of mux_4to1 is begin MUX : process (D, Sel, EN) begin if (EN = '1') then case (Sel) is when "00" => Y <= D(0); when "01" => Y <= D(1); when "10" => Y <= D(2); when "11" => Y <= D(3); when others => Y <= 'Z'; end case; else Y <= 'Z'; end if; end process MUX; end architecture mux_4to1_arch; • Multiplexers in VHDL- Behavioral Model w/ EN

  24. Demultiplexer • Demultiplexer- this is the exact opposite of a Mux- a single input will be routed to a particular output pin depending on the Select settingex) truth table of DemultiplexerSelY0 Y1 0 In 0 1 0 In

  25. Demultiplexer • Demultiplexer- we can again use the behavior of an AND gate to “pass” or “block” the input signal- an AND gate is used for each Demux output

  26. Demultiplexer • Demultiplexers in VHDL- Structural Model entity demux_1to4 is port (D : in STD_LOGIC; Sel : in STD_LOGIC_VECTOR (1 downto 0); EN : in STD_LOGIC; Y : out STD_LOGIC_VECTOR (3 downto 0)); end entity demux_1to4; architecture demux_1to4_arch of demux_1to4 is signal Sel_n : STD_LOGIC_VECTOR (1 downto 0); component inv1 port (In1: in STD_LOGIC; Out1: out STD_LOGIC); end component; component and4 port (In1,In2,In3,In4: in STD_LOGIC; Out1: out STD_LOGIC); end component; begin U1 : inv1 port map (In1 => Sel(0), Out1 => Sel_n(0)); U2 : inv1 port map (In1 => Sel(1), Out1 => Sel_n(1)); U3 : and4 port map (In1 => D, In2 => Sel_n(1), In3 => Sel_n(0), In4 => EN, Out1 => Y(0)); U4 : and4 port map (In1 => D, In2 => Sel_n(1), In3 => Sel(0), In4 => EN, Out1 => Y(1)); U5 : and4 port map (In1 => D, In2 => Sel(1), In3 => Sel_n(0), In4 => EN, Out1 => Y(2)); U6 : and4 port map (In1 => D, In2 => Sel(1), In3 => Sel(0), In4 => EN, Out1 => Y(3)); end architecture demux_1to4_arch;

  27. Demultiplexer entity demux_1to4 is port (D : in STD_LOGIC; Sel : in STD_LOGIC_VECTOR (1 downto 0); EN : in STD_LOGIC; Y : out STD_LOGIC_VECTOR (3 downto 0)); end entity demux_1to4; architecture demux_1to4_arch of demux_1to4 is begin DEMUX : process (D, Sel, EN) begin if (EN = '1') then case (Sel) is when "00" => Y <= 'Z' & 'Z' & 'Z' & D; when "01" => Y <= 'Z' & 'Z' & D & 'Z'; when "10" => Y <= 'Z' & D & 'Z' & 'Z'; when "11" => Y <= D & 'Z' & 'Z' & 'Z'; when others => Y <= "ZZZZ"; end case; else Y <= "ZZZZ"; end if; end process DEMUX; end architecture demux_1to4_arch; • Demultiplexers in VHDL- Behavioral Model with High Z Outputs

  28. Tri-State Buffers • Tri-State Buffers- Provides either a Pass-Through or High Impedance Output depending on Enable Line- High Impedance (Z) allows the circuit to be connected to a line with multiple circuits driving/receiving- Using two Tri-State Buffers creates a "Bus Transceiver" - This is used for "Multi-Drop" Buses (i.e., many Drivers/Receivers on the same bus)ex) truth table of Tri-State Buffer ex) truth table of Bus Transceiver ENB Out Tx/RxMode 0 Z 0 Receive from Bus (Rx) 1 In 1 Drive Bus (Tx)

  29. Tri-State Buffers • Tri-State Buffers in VHDL- 'Z' is a resolved value in the STD_LOGIC data type defined in Package STD_LOGIC- Z & 0 = 0- Z & 1 = 1- Z & L = L- Z & H = H TRISTATE: process (In1, ENB) begin if (ENB = '1') then Out1 <= 'Z'; else Out1 <= In1; end if; end process TRISTATE;

  30. Comparators • Comparators- a circuit that compares digital values (i.e., Equal, Greater Than, Less Than)- we are considering Digital Comparators (Analog comparators also exist)- typically there will be 3-outputs, of which only one is asserted- whether a bit is EQ, GT, or LT is a Boolean expression - a 2-Bit Digital Comparator would look like: (A=B) (A>B) (A<B) A B EQ GT LT 0 0 1 0 0 EQ = (AB)' 0 1 0 0 1 GT = A·B' 1 0 0 1 0 LT = A'·B 1 1 1 0 0

  31. Comparators • Non-Iterative Comparators- "Iterative" refers to a circuit make up of identical blocks. The first block performs its operation which produces a result used in the 2nd block and so on. - this can be thought of as a "Ripple" effect- Iterative circuits tend to be slower due to the ripple, but take less area- Non-Iterative circuits consist of combinational logic executing at the same time"Equality" - since each bit in a vector must be equal, the outputs of each bit's compare can be AND'd - for a 4-bit comparator: EQ = (A3B3)' · (A2B2)' ·(A1B1)' ·(A0B0)'

  32. Comparators • Non-Iterative Comparators"Greater Than" - we can start at the MSB (n) and check whether An>Bn. - If it is, we are done and can ignore the rest of the LSB's. - If it is NOT, but they are equal, we need to check the next MSB bit (n-1) - to ensure the previous bit was equal, we include it in the next LSB's logic expression:Steps - GT = An·Bn' (this is ONLY true if An>Bn)- if it is NOT GT, we go to the n-1 bit assuming that An= Bn (An Bn)' - we consider An-1>Bn-1 only when An= Bn[i.e., (An Bn)' · (An-1·Bn-1') ] - we continue this process through all of the bits - 4-bit comparator GT = (A3·B3') + (A3B3)' ·(A2·B2') +(A3B3)' ·(A2B2)' ·(A1·B1') +(A3B3)' ·(A2B2)' ·(A1B1)' ·(A0·B0')

  33. Comparators • Non-Iterative Comparators"Less Than" - since we assume that if the vectors are either EQ, GT, or LT, we can create LT using: LT = EQ' · GT' • Iterative Comparators- we can build an iterative comparator by passing signals between identical modules from MSB to LSB ex) module for 1-bit comparatorEQout = (AB)' · EQin- EQout is fed into the EQin port of the next LSB module- the first iterative module has EQin set to '1'

  34. Comparators • Comparators in VHDL- Structural Model entity comparator_4bit is port (In1, In2 : in STD_LOGIC_VECTOR (3 downto 0); EQ, LT, GT : out STD_LOGIC); end entity comparator_4bit; architecture comparator_4bit_arch of comparator_4bit is signal Bit_Equal : STD_LOGIC_VECTOR (3 downto 0); signal Bit_GT : STD_LOGIC_VECTOR (3 downto 0); signal In2_n : STD_LOGIC_VECTOR (3 downto 0); signal In1_and_In2_n : STD_LOGIC_VECTOR (3 downto 0); signal EQ_temp, GT_temp : STD_LOGIC; component xnor2 port (In1,In2: in STD_LOGIC; Out1: out STD_LOGIC); end component; component or4 port (In1,In2,In3,In4: in STD_LOGIC; Out1: out STD_LOGIC); end component; component nor2 port (In1,In2: in STD_LOGIC; Out1: out STD_LOGIC); end component; component and2 port (In1,In2: in STD_LOGIC; Out1: out STD_LOGIC); end component; component and3 port (In1,In2,In3: in STD_LOGIC; Out1: out STD_LOGIC); end component; component and4 port (In1,In2,In3,In4: in STD_LOGIC; Out1: out STD_LOGIC); end component; component inv1 port (In1: in STD_LOGIC; Out1: out STD_LOGIC); end component;

  35. Comparators • Comparators in VHDL Cont… begin -- "Equal" Circuitry XN0 : xnor2 port map (In1(0), In2(0), Bit_Equal(0)); -- 1st level of XNOR tree XN1 : xnor2 port map (In1(1), In2(1), Bit_Equal(1)); XN2 : xnor2 port map (In1(2), In2(2), Bit_Equal(2)); XN3 : xnor2 port map (In1(3), In2(3), Bit_Equal(3)); AN0 : and4 port map (Bit_Equal(0), Bit_Equal(1), Bit_Equal(2), Bit_Equal(3), Eq); -- 2nd level of "Equal" Tree AN1 : and4 port map (Bit_Equal(0), Bit_Equal(1), Bit_Equal(2), Bit_Equal(3), Eq_temp); -- "Greater Than" Circuitry IV0 : inv1 port map (In2(0), In2_n(0)); -- creating In2' IV1 : inv1 port map (In2(1), In2_n(1)); IV2 : inv1 port map (In2(2), In2_n(2)); IV3 : inv1 port map (In2(3), In2_n(3)); AN2 : and2 port map (In1(3), In2_n(3), In1_and_In2_n(3)); -- creating In1 & In2' AN3 : and2 port map (In1(2), In2_n(2), In1_and_In2_n(2)); AN4 : and2 port map (In1(1), In2_n(1), In1_and_In2_n(1)); AN5 : and2 port map (In1(0), In2_n(0), In1_and_In2_n(0)); AN6 : and2 port map (Bit_Equal(3), In1_and_In2_n(2), Bit_GT(2)); AN7 : and3 port map (Bit_Equal(3), Bit_Equal(2), In1_and_In2_n(1), Bit_GT(1)); AN8 : and4 port map (Bit_Equal(3), Bit_Equal(2), Bit_Equal(1), In1_and_In2_n(0), Bit_GT(0)); OR0 : or4 port map (In1_and_In2_n(3), Bit_GT(2), Bit_GT(1), Bit_GT(0), GT); OR1 : or4 port map (In1_and_In2_n(3), Bit_GT(2), Bit_GT(1), Bit_GT(0), GT_temp); -- "Less Than" Circuitry ND0 : nor2 port map (EQ_temp, GT_temp, LT); end architecture comparator_4bit_arch;

  36. Comparators • Comparators in VHDL- Behavioral Model entity comparator_4bit is port (In1, In2 : in STD_LOGIC_VECTOR (3 downto 0); EQ, LT, GT : out STD_LOGIC); end entity comparator_4bit; architecture comparator_4bit_arch of comparator_4bit is begin COMPARE : process (In1, In2) begin EQ <= '0'; LT <= '0'; GT <= '0'; -- initialize outputs to '0' if (In1 = In2) then EQ <= '1'; end if; -- Equal if (In1 < In2) then LT <= '1'; end if; -- Less Than if (In1 > In2) then GT <= '1'; end if; -- Greater Than end process COMPARE; end architecture comparator_4bit_arch;

  37. Ripple Carry Adder • Addition – Half Adder- one bit addition can be accomplished with an XOR gate (modulo sum 2) 0 1 0 1 +0+0+1+1 0 1 1 10- notice that we need to also generate a “Carry Out” bit- the “Carry Out” bit can be generated using an AND gate- this type of circuit is called a “Half Adder”- it is only “Half” because it doesn’t consider a “Carry In” bit

  38. Ripple Carry Adder • Addition – Full Adder- to create a full adder, we need to include the “Carry In” in the SumCin A BCoutSum 0 0 0 0 0 0 0 1 0 1 Sum = A  B  Cin 0 1 0 0 1 Cout = Cin∙A + A∙B + Cin∙B 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1- you could also use two "Half Adders" to accomplish the same thing

  39. Ripple Carry Adder • Addition – Ripple Carry Adder- cascading Full Adders together will allow the Cout’s to propagate (or Ripple) through the circuit- this configuration is called a Ripple Carry Adder

  40. Ripple Carry Adder • Addition – Ripple Carry Adder- What is the delay through the Full Adder? - Each Full Adder has the following logic: Sum = A  B  CinCout = Cin∙A + A∙B + Cin∙B - tFull-Adder will be the longest combinational logic delay path in the adder

  41. Ripple Carry Adder • Addition – Ripple Carry Adder- What is the delay through the entire iterative circuit? - Each Full Adder has the following logic:tRCA = n·tFull-Adder- the delay increases linearly with the number of bits - different topologies within the full-adder to reduce delay (Δt) will have a n·Δt effect

  42. Carry Look Ahead Adders • Addition – Carry Look Ahead Adder- We've seen a Ripple Carry Adder topology (RCA)- this is good for simplicity and design-reuse- however, the delay increases linearly with the number of bitstRCA = n·tFull-Adder- different topologies within the full-adder to reduce delay (Δt) will have a n·Δt effect - the linear increase in delay comes from waiting for the Carry to Ripple through

  43. Carry Look Ahead Adders • Addition – Carry Look Ahead Adder- to avoid the ripple, we can build a Carry Look-Ahead Adder (CLA)- this circuit calculates the carry for all Full-Adders at the same time- we define the following intermediate stages of a CLA:Generate "g", an adder (i) generates a carry out (Ci+1)under input conditions Ai and Bi independent of Ai-1, Bi-1, or Carry In (Ci) Ai Bi Ci+10 0 00 1 0 we can say that: gi = Ai·Bi1 0 01 1 1 remember, g does NOT consider carry in (Ci)

  44. Carry Look Ahead Adders • Addition – Carry Look Ahead AdderPropagate "p", an adder (i) will propagate (or pass through) a carry in (Ci)depending on input conditions Ai and Bi,:Ci Ai Bi Ci+10 0 0 00 0 1 0 pi is defined when there is a carry in,0 1 0 0 so we ignore the row entries where Ci=00 1 1 1 1 0 0 0 if we only look at the Ci=1 rows 1 0 1 1 we can say that: 1 1 0 1 pi = (Ai+Bi)·Ci1 1 1 1

  45. Carry Look Ahead Adders • Addition – Carry Look Ahead Adder - said another way, Adder(i) will "Generate" a Carry Out (Ci+1) if:gi = Ai·Bi and it will "Propagate" a Carry In (Ci) when pi = (Ai+Bi)·Ci- a full expression for the Carry Out (Ci+1) in terms of p and g is given by: Ci+1 = gi+pi·Ci- this is good, but we still generate Carry's dependant on previous stages (i-1) of the iterative circuit

  46. Carry Look Ahead Adders • Addition – Carry Look Ahead Adder - We can eliminate this dependence by recursively expanding each Carry Equation ex) 4 bit Carry Look Ahead Logic C1 = g0+p0·C0 (2-Level Product-of-Sums) C2 = g1+p1·C1 C2 = g1+p1·(g0+p0·C0) C2 = g1+p1·g0+p1·p0·C0 (2-Level Product-of-Sums) C3 = g2+p2·C2 C3 = g2+p2·(g1+p1·g0+p1·p0·C0) C3 = g2+p2·g1+p2·p1·g0+p2·p1·p0·C0 (2-Level Product-of-Sums)C4 = g3+p3·C3C4 = g3+p3·(g2+p2·g1+p2·p1·g0+p2·p1·p0·C0)C4 = g3+p3·g2+p3·p2·g1+p3·p2·p1·g0+p3·p2·p1·p0·C0 (2-Level Product-of-Sums)- this gives us logic expressions that can generate a next stage carry based upon ONLY the inputs to the adder and the original carry in (C0)

  47. Carry Look Ahead Adders • Addition – Carry Look Ahead Adder - the Carry Look Ahead logic has 3 levels 1) g and p logic 2) product terms in the Ci equations 3) sum terms in the Ci equations- the Sum bits require 2 levels of Logic 1) AiBiCiNOTE: A Full Adder made up of 2 Half Adders has 3 levels. But the 3rd level is used in the creation of the Carry Out bit. Since we do not use it in a CLA, we can ignore that level.- So a CLA will have a total of 5 levels of Logic

  48. Carry Look Ahead Adders • Addition – Carry Look Ahead Adder - the 5 levels of logic are fixed no matter how many bits the adder is (really?)- In reality, the most significant Carry equation will have i+1 inputs into its largest sum/product term - this means that Fan-In becomes a problem since real gates tend to not have more than 4-6 inputs- When the number of inputs gets larger than the Fan-In, the logic needs to be broken into another level ex) A+B+C+D+E = (A+B+C+D)+E- In the worst case, the logic Fan-In would be 2. Even in this case, the delay associated with the Carry Look Ahead logic would be proportional to log2(n)- Area and Power are also concerns with CLA's. Typically CLA's are used in computationally intense applications where performance outweighs Power and Area.

  49. Carry Look Ahead Adders • Adders in VHDL- (+) and (-) are not defined for STD_LOGIC_VECTOR- The Package STD_LOGIC_ARITH gives two data types: UNSIGNED (3 downto 0) := "1111"; -- +15 SIGNED (3 downto 0) := "1111"; -- -1- these are still resolved types (STD_LOGIC), but the equality and arithmetic operations are slightly different depending on whether you are using Signed vs. Unsigned • Considerations- when adding signed and unsigned numbers, the type of the result will dictate how the operands are handled/converted- if assigning to an n-bit, SIGNED result, an n-1 UNSIGNED operand will automatically be converted to signed by extending its vector length by 1 and filling it with a sign bit (0)

  50. Carry Look Ahead Adders • Adders in VHDLex) A,B : in UNSIGNED (7 downto 0); C : in SIGNED (7 downto 0); D : in STD_LOGIC_VECTOR (7 downto 0); S : out UNSIGNED (8 downto 0); T : out SIGNED (8 downto 0); U : out SIGNED (7 downto 0); S(7 downto 0) <= A + B; -- 8-bit UNSIGNED addition, not considering Carry S <= ('0' & A) + ('0' & B); -- manually increasing size of A and B to include Carry. Carry will be kept in S(9) T <= A + C; -- T is SIGNED, so A's UNSIGNED vector size is increased by 1 and filled with '0' as a sign bit U <= C + SIGNED(D); -- D is converted (considered) to SIGNED, not increased in size U <= C + UNSIGNED(D); -- D is converted (considered) to UNSIGNED, not increased in size

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