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Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering

ELEC 5200-001/6200-001 Computer Architecture and Design Spring 2009 Control Unit: Hard-Wired and Microcoded (Chapter 4). Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 http://www.eng.auburn.edu/~vagrawal

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Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering

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  1. ELEC 5200-001/6200-001Computer Architecture and DesignSpring 2009 Control Unit: Hard-Wiredand Microcoded (Chapter 4) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu ELEC 5200-001/6200-001 Lecture 8

  2. Alternatives for Control Unit (CU) • Hard-wired (hardware) • Random logic, programmable logic array (PLA), or ROM • Fast • Inflexible • Firmware • Microprogrammed or microcoded CU • Control implemented like a computer (microcomputer) • Microinstructions • Microprogram • Flexible • Software-like changes to instruction set possible • Completely different instruction sets can be emulated • Speed limited by microcomputer memory ELEC 5200-001/6200-001 Lecture 8

  3. Hardwired CU: Single-Cycle • Implemented by combinational logic. Control logic Datapath 6 funct. code Control signals To ALU 6 opcode 3 ALU control 2 ALUOp ELEC 5200-001/6200-001 Lecture 8

  4. Jump 0-25 Shift left2 0 mux 1 4 Add 1 mux 0 ALU Branch opcode MemtoReg CONTROL 26-31 RegWrite ALUSrc 21-25 zero MemWrite MemRead ALU Instr. mem. PC Reg. File Data mem. 1 mux 0 16-20 0 mux 1 1 mux 0 11-15 Single-cycle Datapath RegDst ALUOp ALU Cont. Sign ext. Shift left 2 0-15 0-5 ELEC 5200-001/6200-001 Lecture 8

  5. Single-Cycle Control Logic Op5 Op4 Op3 Op2 Op1 Op0 ALUOp1 MemtoReg MemRead ALUOp0 MemWrite RegWrite Jump Branch RegDst ALUSrc ELEC 5200-001/6200-001 Lecture 8

  6. Single-Cycle Control Circuit Op5 Op4 Op3 Op2 Op1 Op0 lw R sw beq J RegDst ALUSrc MemtoReg RegWrite MemRead MemWrite Branch ALUOp1 ALUOp0 Jump ELEC 5200-001/6200-001 Lecture 8

  7. ALU Control Logic ELEC 5200-001/6200-001 Lecture 8

  8. ALU Control Operation select from control From Control Circuit ALUOp1 ALUOp0 3 zero ALU result F3 F2 F1 F0 overflow Function code Operation select ALU function 000 AND 001 OR 010 Add 110 Subtract 111 Set on less than ELEC 5200-001/6200-001 Lecture 8

  9. Multicycle Datapath PCSource PCWrite etc. Shift left 2 26-31 to Control FSM 0-25 RegWrite 21-25 28-31 16-20 Instr. reg. (IR) A Reg. PC Addr. 11-15 Memory ALU Register file ALUSrcA ALUSrcB ALUOut Reg. IorD Data Mem. Data (MDR) B Reg. RegDst IRWrite 4 MemRead Sign extend Shift left 2 MemtoReg 0-15 MemWrite ALU control ALUOp 0-5 ELEC 5200-001/6200-001 Lecture 7

  10. Instr. decode/reg. fetch/branch addr. Instr. fetch/ adv. PC ALU operation Write PC on branch condition Write jump addr. to PC Compute memory addr. Write memory data Read memory data Write register Write register Multicycle Control FSM Inputs: 6 opcode bits Outputs: 16 control signals Start State 0 1 lw or sw J R B 3 2 lw 6 8 9 sw 4 5 7 ELEC 5200-001/6200-001 Lecture 8

  11. States and Outputs • Suppose 10 states are encoded 0000 through 1001. • State code completely determines 16 control signals (Moore machine). • States 0 (0000), 3 (0011) and 6 (0110) • Next state ← present state + 1 • State 1 (0001) – opcode determines next state • State 2 (0010) for lw or sw • State 6 (0110) for R-type of instruction • State 8 (1000) for branch instruction • State 9 (1001) for jump instruction • State 2 (0010) – opcode determines next state • State 3 (0011) for lw • State 5 (0101) for sw • States 4 (0100), 5 (0101), 7 (0111), 8 (1000) and 9 (1001) – next state is unconditionally 0 (0000) ELEC 5200-001/6200-001 Lecture 8

  12. Instr. decode/reg. fetch/branch addr. Instr. fetch/ adv. PC ALU operation Read memory data A Program-Like Implementation Inputs: 6 opcode bits Outputs: 16 control signals Start State 0000 0001 lw or sw J R 0011 B 0010 lw Compute memory addr. Write PC on branch condition Write jump addr. to PC 0110 sw 1000 1001 0100 0101 0111 Write memory data Write register Write register ELEC 5200-001/6200-001 Lecture 8

  13. Implementing with ROM Control PLA or ROM 16 words 16 16 control signals 2 PLA input or ROM address Select one of 4 ways 4 Four flip-flops State sequencer 6-bit opcode 6 ELEC 5200-001/6200-001 Lecture 8

  14. ROM and State Sequencer Control ROM Sixteen 18-bit words 4-bit address 16 Control signals to datapath 2 0001 AddrCtl go to 00 st. 0 11 st. + 1 01 st. 2,6,8,9 10 st. 3,5 Address 4 4-bit state flip-flops 4 MUX 11 10 01 00 Adder Advance state 0000 4 Dispatch ROM 2 Dispatch ROM 1 6-bit Opcode from IR sw or lw ROM Address sw, lw, R, B or J 6 ELEC 5200-001/6200-001 Lecture 8

  15. Dispatch ROM Contents Each dispatch ROM has sixty-four 4-bit words Address is 6-bit opcode Content is next state (4-bits) ELEC 5200-001/6200-001 Lecture 8

  16. Control ROM Contents • Control ROM has sixteen 18-bit words: • bits 0-1, AddrCtl to control mux • bits 2-17, sixteen control signals for datapath • Address is 4-bit state of control machine ELEC 5200-001/6200-001 Lecture 8

  17. Microprogram: Basic Idea • The control unit in a computer generates an output (sequence of control signals) for each instruction. • Suppose we break down each instruction into a series of smaller operations (microinstructions), such as, fetch, decode, etc. • Then, implement the control unit as a smallcomputer (within the computer) that executes a sequence of microinstructions (microprogram) for each instruction. • M. V. Wilkes, “The Best Way to Design an Automatic Calculating Machine,” Report of Manchester University Computer Inaugural Conference, pp. 16-18, 1951. Reprinted in E. E. Swartzlander (editor), Computer Design Development: Principal Papers, pp. 266-270, Rochelle Park, NJ: Hayden, 1976. ELEC 5200-001/6200-001 Lecture 8

  18. Maurice V. Wilkes Born June 26, 1913, Staffordshire, UK 1967 Turing Award citation: Professor Wilkes Is best known as the builder and designer of the EDSAC, the first computer with an internally stored program. Built in 1949, the EDSAC used a mercury delay line memory. He is also known as the author, with Wheeler and Gill, of a volume on “Preparation of Programs for Electronic Digital Computers” in 1951, in which program libraries were effectively introduced. ELEC 5200-001/6200-001 Lecture 8

  19. Microcoded Control Unit Microcode word Sixteen 18-bit words 4-bit address Microcode memory 16 Control signals to datapath 0001 AddrCtl Address Sequencing field 2 4 μPC 4-bit state flip-flops 4 MUX 11 10 01 00 Adder 0000 Dispatch ROM 2 Dispatch ROM 1 Opcode from IR Address select logic lw or sw sw, lw, R, B or J ROM address 6 ELEC 5200-001/6200-001 Lecture 8

  20. Implementing the Idea • Use a memory type implementation for control unit. • Create a software infrastructure to automatically translate instructions into memory data (microcode): • Microinstructions – define a machine language in which instructions can be described • Microprogram – an instruction described as a sequence of microinstructions • Microassembler – converts microprogram to (binary) microcode • Is there a micro-compiler? ELEC 5200-001/6200-001 Lecture 8

  21. Microprogramming • A microinstruction set is defined. • To program the control of a computer for an instruction set, a programmer writes a microprogram for each machine instruction. • Each micrprogram is converted into microcode, specific to the datapath hardware, by a microassembler and the entire microcode is loaded in the microcode memory of the control unit (CU). ELEC 5200-001/6200-001 Lecture 8

  22. Breaking Up MIPS Instructions • R-type instruction: • Fetch • Decode • ALU operation • Write register • lw: • Fetch • Decode • Memory address computation • Read memory • Write register ELEC 5200-001/6200-001 Lecture 8

  23. Microinstructions for MIPS ISA • Fetch fetch instruction • Decode decode, read registers, calculate branch address • RegWr write register • MEM1 compute memory address • LW2 memory read • SW2 memory write • R1 register type execution • BEQ1 branch execution • JUMP1 jump execution ELEC 5200-001/6200-001 Lecture 8

  24. Let’s Construct MIPS Instructions • R-type instruction: • Fetch • Decode • R1 • RegWr • lw: • Fetch • Decode • MEM1 • LW1 • RegWr • sw: • Fetch • Decode • MEM1 • SW1 • Branch: • Fetch • Decode • BEQ1 • Jump: • Fetch • Decode • JUMP1 ELEC 5200-001/6200-001 Lecture 8

  25. Microinstruction Format • Label or name of microinstruction, e.g., Fetch, MEM1, etc. • Seven argument fields • ALU control add, subtract or funct. code # result to ALUOut • SRC1 PC or A • SRC2 B, 4, extend or extend-shift • Reg. control Read # read two reg. specified by IR into A and B Write ALU # write ALUOut to register file Write MDR # register file ← MDR • Memory Read PC # IR ← M[ PC ] Read ALU # MDR ← M[ ALUOut ] Write ALU # M[ ALUOut ] ← B • PCWrite ALU # write PC from ALU ALU cond. # If zero = 1, PC ← ALUOut Jump addr. # PC ← jump address • Sequencing Seq # choose next μInst. Sequentially fetch # go to first μInst. to begin new instr. Dispatch i # use Dispatch ROM i, i = 1 or 2 ELEC 5200-001/6200-001 Lecture 8

  26. Instr. decode/reg. fetch/branch addr. Instr. fetch/ adv. PC ALU operation Write PC on branch condition Write jump addr. to PC Compute memory addr. Write memory data Read memory data Write register Write register Sequencing Illustrated Fetch 1 Sequencing = seq State 0 Fetch Dispatch 1 LW2 3 2 Mem1 R1 lw 6 8 Dispatch 2 seq 9 seq SW2 4 5 JUMP1 7 BEQ1 Fetch ELEC 5200-001/6200-001 Lecture 8

  27. Microinstruction Arguments ELEC 5200-001/6200-001 Lecture 8

  28. Microinstruction Arguments (Cont.) ELEC 5200-001/6200-001 Lecture 8

  29. Microinstruction Arguments (Cont.) ELEC 5200-001/6200-001 Lecture 8

  30. Microinstruction Fetch Label ALU SRC1 SRC2 Reg. Mem. PCWrite Seq. ctrl. ctrl. ctrl. Fetch Add PC 4 Read PC ALU Seq Decode Add PC ExtShft Read Dispatch 1 Microassembler produces the following microcode: 00 0 01 0 0 0 1 0 1 0 00 1 0 11 00 0 11 0 0 0 0 0 0 0 00 0 0 01 MemRead IorD IRWrite MemWrite RegWrite RegDst MemtoReg PCSource PCWrite PCWriteCond ALUOp Addrctl ALUSrcA ALUSrcB ELEC 5200-001/6200-001 Lecture 8

  31. Microprogram for lw and sw Label ALU SRC1 SRC2 Reg. Mem. PCWrite Seq. ctrl. ctrl. ctrl. Mem1 Add A Extend Dispatch 2 LW2 Read ALU Seq RegWr Write MDR Fetch SW2 Write ALU Fetch Microprogram consists of four microinstructions. ELEC 5200-001/6200-001 Lecture 8

  32. Microprogram for R-Type Instruction Label ALU SRC1 SRC2 Reg. Mem. PCWrite Seq. ctrl. ctrl. ctrl. R1 Funct code A B Seq RegWr Write ALU Fetch Go to next μInstr. Go to μInstr. Fetch Microprogram consists of two microinstructions. ELEC 5200-001/6200-001 Lecture 8

  33. Microprogram for beq Instruction Label ALU SRC1 SRC2 Reg. Mem. PCWrite Seq. ctrl. ctrl. ctrl. BEQ1 Subt A B ALUOut-condFetch If (zero) then PC ← ALUOutGo to μInstr. Fetch Microprogram consists of one microinstruction. ELEC 5200-001/6200-001 Lecture 8

  34. Microprogram for jump Instruction Label ALU SRC1 SRC2 Reg. Mem. PCWrite Seq. ctrl. ctrl. ctrl. JUMP1 Jump addressFetch Microprogram consists of one microinstruction. ELEC 5200-001/6200-001 Lecture 8

  35. μProgram for Multi-Cycle CU Label ALU SRC1 SRC2 Reg. Mem. PCWrite Seq. ctrl. ctrl. ctrl. Fetch Add PC 4 Read PC ALU Seq Decode1 Add PC ExtShft Read Disp. 1 Mem1 Add A Extend Disp. 2 LW2 Read ALU Seq RegWr Write MDR Fetch SW2 Write ALU Fetch R1 FntCd. A B Seq RegWr Write ALU Fetch BEQ1 Subt A B ALUOut-cond Fetch JUMP1 Jump address Fetch ELEC 5200-001/6200-001 Lecture 8

  36. Multicycle Datapath PCSource PCWrite etc. Shift left 2 26-31 to MicrocodedControl 0-25 RegWrite 21-25 28-31 16-20 Instr. reg. (IR) A Reg. PC Addr. 11-15 Memory ALU Register file ALUSrcA ALUSrcB ALUOut Reg. IorD Data Mem. Data (MDR) B Reg. RegDst IRWrite 4 MemRead Sign extend Shift left 2 MemtoReg 0-15 MemWrite ALU control ALUOp 0-5 ELEC 5200-001/6200-001 Lecture 7

  37. Microcode Operation • μPC is always initialized to 0000 • Load starting instruction address in PC • Clock control and datapath ELEC 5200-001/6200-001 Lecture 8

  38. How Microcode Works Sixteen 18-bit words 4-bit address Microcode memory 16 clk 1: Set Datapath for Fetch 0001 in clk 2 0001 AddrCtl μPC Address Sequencing field 4 0000 11 4 MUX 11 10 01 00 Adder 0000 Opcode from IR In clk 2 Dispatch ROM 2 Dispatch ROM 1 Address select logic lw or sw sw, lw, R, B or J ROM address 6 ELEC 5200-001/6200-001 Lecture 8

  39. Summary • Hard-wired control: A finite state machine implemented typically using programmable logic array (PLA) or random logic. • Microinstruction: A one-clock instruction that asserts a set of control signals to the datapath and specifies what microinstruction to execute next. • Microprogram: A sequence of microinstructions that implements a multicycle (or single cycle) instruction. • Microcode: Machine code of a microprogram, generally produced by a microassembler. • Microprogrammed or microcoded control: A method of specifying control that uses microcode rather than a finite state machine. ELEC 5200-001/6200-001 Lecture 8

  40. Further on Microprogramming • Preceding discussion is based on: • D. A. Patterson and J. L. Hennessey, Computer Organization and Design, Second Edition, San Francisco: Morgan-Kaufman, 1998, Chapter 5, pp. 399-410. • Terms “microcomputer” and “microarchitecture” are not related to microprogramming. • Nanoprogramming: Two levels of microprogramming – a “recursive” control: • Nanodata Corp., QM-1 Hardware Level Users Manual, 2nd Ed., Williamsville, NY, 1972. • J. P. Hayes, Computer Architecture and Organization, Section 4.4.3, NY: McGraw-Hill, 1978. • Virtual machines: Any program can be run on any instruction set using an interpreter. Example, Java. ELEC 5200-001/6200-001 Lecture 8

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