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Sistemi Elettronici Programmabili

Sistemi Elettronici Programmabili. ST7 Generalità e core. SUPPORT. FLASH MEMORY. ST7 Core. STM DEVELOPMENT TOOLS. 3rd PARTY DEVELOPMENT TOOLS. ANALOG. DIGITAL. EMC/LOW POWER. SERVICE. THE ST7 VISION. $00. PERIPHERALS HARDWARE REGISTERS. $80. RAM. STACK. $0200. RESERVED.

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Sistemi Elettronici Programmabili

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  1. Sistemi Elettronici Programmabili ST7Generalità e core Sistemi Elettronici Programmabili

  2. SUPPORT FLASH MEMORY ST7 Core STM DEVELOPMENT TOOLS 3rd PARTY DEVELOPMENT TOOLS ANALOG DIGITAL EMC/LOW POWER SERVICE THE ST7 VISION Sistemi Elettronici Programmabili

  3. $00 PERIPHERALS HARDWARE REGISTERS $80 RAM STACK $0200 RESERVED $1000 ROM/EPROM up to 60 KBytes $FFE0 INTERRUPTS & RESET VECTORS $FFFF THE ST7 CORE • Well-known Industry Standard 8-bit CISC architecture (Von Neuman) • compatible with most popular cores • 200 ns minimum instruction time with 1.375µs 8x8 multiplication • 64 KBytes linear addressing memory • Indirect and Y index memory access • Direct STACK management • And many powerful added features ... Sistemi Elettronici Programmabili

  4. STM A KEY PLAYER IN FLASH MEMORY FLASH A VOLUME SUPPLIER Micros with embedded non-volatile memoryhave been in high volume production since 1998 Non-volatile memory products : 1 Billion units sold in 1998 MASTERING EMBEDDED FLASH SOLUTIONS Very high reliability with 20 year retention Two solutions for cost vs. feature optimization eFLASH Data EEPROM capable Flash Sistemi Elettronici Programmabili

  5. ST7 FLASH : IN SITU PROGRAMMING WITH HIGH PROTECTION • Patented high protection level on Flash, OTP and ROM versions Piracy protection Unexpected writing protection • In-situ programming for Flash and EEPROM from any pins / peripheral interfaces (software configurable) Standalone mode (application running) Remote mode (at production level) Flexible production manufacturing and test flow On-the-fly application reprogramming Sistemi Elettronici Programmabili

  6. - + ST7 ANALOG PERIPHERALS MORE FLEXIBILITY & LESS COMPONENTS Low Voltage Detector Op Amp 8- & 10-bit ADC ... and more to come • Up to 16 channels • Fast conversion time 3 ms • High resolution (5 mV) Simple PCB No interrupt Less external components Low power consumption Less external components Embedded supply monitoring Sistemi Elettronici Programmabili

  7. interrupt generation interrupt generation VCC supply VLVDr(IT) hysteresis VLVDf(IT) fixed DV VLVDr (reset) hysteresis hysteresis VLVDf(reset) VDD Min Internal RESET LOW VOLTAGE DETECTOR CHARACTERISTICS • LVD (IT) : interrupt generation before entering reset • LVD (reset) : flag activation • Selectable reset levels for • 5 V applications : [4.5 V - 5.5 V] • 3.3 V applications : [3 V - 3.6 V] • ... Context saving in EEPROM Origin of reset localizable Saves external supply monitoring circuitry Sistemi Elettronici Programmabili

  8. VDD ST7 Reset circuit LOW VOLTAGE DETECTOR External components saved • 2 Clamping diodes • 4 Resistors • 1 Transistor • 1 Zener diode • 1 Filter capacitor • Integrated 3-level range on Low Voltage Detector • Reset automatically activates when 0.8V < VDD < Safe Level • External reset generation (30 µs) • Internal interrupt & reset generation Reset of other devices of the application • Cost savings of 10 to 15 cents Enhanced reliability Safe micro behavior Sistemi Elettronici Programmabili

  9. ST7 PROGRAMMABLE GAIN OP-AMP ADC OUTPUT Op-Amp - ANALOG / DIGITAL OUTPUT + PROGRAMMABLE VREF INTEGRATED OPERATIONAL AMPLIFIER • Rail-to-rail programmable op-amp • Band gap • Fixed voltage reference • Programmable voltage reference • 6.5 MHz bandwidth • Auto-zero mode • On/off capability • Internal connection to ADC • Can be used for • ADC zooming • Comparator / voltage threshold detector • Peak voltage detector ADC error suppression Low power consumption Cost saving Sistemi Elettronici Programmabili

  10. 2 mA RUN 3 KV SLOW ST7 PRODUCT RANGE 2 KV WAIT INTERNAL SAFE OSCILLATOR Industry Acceptance SLOW-WAIT 1 KV ACTIVE-HALT 98 99 00 HALT 0.2 mA ST7 LOW POWER SOLUTIONS EMC by design Oscillator Low power modes Low emission High robustness < 700 mA / 16 MHz Low power and safe Low power consumption Sistemi Elettronici Programmabili

  11. osc1 osc2 osc1 osc2 osc1 osc2 osc2 osc1 ST7 MULTI-OSCILLATOR SYSTEM osc1 osc2 • Quartz / ceramic • Up to 16 MHz • Internal RC • 1 MHz +/- 1% • 4 MHz +/- 20% • External source • Up to 16 MHz • External RC • 1 to 14 MHz • Low frequency backup safety oscillator • Automatic switch from main clock to safe clock • Dedicated flag & Interrupt generation • Watchdog always operational • Internal safe oscillator • 250 KHz +/- 15% Power optimization Safe microcontroller behavior Sistemi Elettronici Programmabili

  12. ST7 LOW POWER MODES RUN SLOW Real Time Clock WAIT SLOW-WAIT ACTIVE-HALT HALT Sistemi Elettronici Programmabili

  13. EMC APPROACH : SECURE & ROBUST • Low power design • Protected and robust macrocells • Factual measurements through comprehensive testing • Operation in noise sensitive environments can be evaluated from the information available in datasheet High protection Cost savings • Fewer components on the board Sistemi Elettronici Programmabili

  14. W REGISTER DATA BUS R R/W REGISTER DATA BUS ALTERNATE INPUT EXTERNAL INTERRUPT INTERRUPT ALTERNATE OUTPUT ANALOG INPUT ST7 PROGRAMMABLE I/Os PIN-BY-PIN FLEXIBLE CONFIGURATION Output I/O port configuration example Input I/O port configuration example • High flexibility in I/Os and software configuration • Fewer external components and less expensive PCB One microcontroller for different design versions Lower development and inventory cost Lower pin count and better pricing through economy of scale Sistemi Elettronici Programmabili

  15. LCD DRIVER SPI I/Os I2C MOTOR CONTROL TIMERS EEPROM CAN ST7 Core SCI (UART) ROM FLASH SRAM Op Amp SMART CARD INT. ADC USB ST7 : A SET OF AVAILABLE PERIPHERALS Sistemi Elettronici Programmabili

  16. Sistemi Elettronici Programmabili

  17. ST7 TECHNICAL TRAINING 1 - INTRODUCTION 2 - CORE 3 - ADRESSING MODES 4 - PERIPHERALS 5 - ST7 SOFTWARE TOOLS 6 - ST7 HARDWARE TOOLS 7 - STVD7 Sistemi Elettronici Programmabili

  18. ST7 CORE ST7 STACK INTERNAL REGISTERS LOW POWER MODES INTERRUPTS CLOCK CONTROLLER RESET SYSTEM LVD MEMORY SPACE WATCHDOG Sistemi Elettronici Programmabili

  19. ST7 CORE General Description • THE ST7 CORE (Von Neuman Architecture) IS BUILT AROUND : • an 8-bit Arithmetic and Logic Unit (ALU) • 6 internal registers : Accumulator (A), X and Y index registers, Program Counter (PC), the Stack Pointer (SP) and the Code Condition register (CC) • a controller block • IT INTERFACES WITH : • an on-chip oscillator • a reset block • address and data buses to access memories and peripherals • an interrupt controller Sistemi Elettronici Programmabili

  20. RESET ST7 COREBlock Diagram OSCin Mutli oscillator Clock controller OSCout Internal CLOCK ISPSEL/ Vpp CONTROL 8 -BIT ALU Watchdog LVD Enhanced Reset SP Accu PCL Index X DATA BUS PCH Index Y CC ADDRESS BUS Program memory RAM Sistemi Elettronici Programmabili

  21. Y is not automatically stacked. If needed, it must be done using the PUSH and POP instructions • Instructions using X are faster than the ones using Y ST7 COREInternal Registers (1) • The ACCUMULATOR is an 8-bit general purpose register used to hold: • Operands • Results of arithmetic and logic operation • The X and Y REGISTERS are two 8-bit registers used to : • Create effective addresses • Store temporary data Sistemi Elettronici Programmabili

  22. ST7 COREInternal Registers (2) • The PROGRAM COUNTER PC is a 16-bit register used to store the address of the next instruction to be executed by the CPU. As a result, the ST7 can address up to 64k of program memory • The STACK POINTER SP is a 16-bit register. The msb is fixed by hardware • The CODE CONDITION CC is a 5-bit register Sistemi Elettronici Programmabili

  23. 7 0 X X X X X X X X RESET VALUES : RESET VALUES : X X X X X X X X 7 0 RESET VALUES : X X X X X X X X 15 7 0 RESET VALUES : RESET VECTOR @ FFFEh-FFFFh 15 7 0 x x x x x x x x Fixed By HW 7 6 5 4 2 1 0 3 1 1 1 H I N Z C RESET VALUES : 1 1 1 1 0 1 0 X ST7 COREInternal Registers (3) ACCUMULATOR : 7 X INDEX REGISTER : 0 Y INDEX REGISTER : PROGRAM COUNTER : STACK POINTER : CONDITION CODE REGISTER : Sistemi Elettronici Programmabili

  24. Lower Address Higher Address ST7 COREStack manipulation (1) • PURPOSE : • Save the CPU context during subroutine calls or interrupts • Save temporary user's data (PUSH and POP instructions) • IN CASE OF OVERFLOW (LOWER LIMIT EXCEEDED) : • SP rolls over to the higher address • Previous value is overwritten so lost • Stack overflow is not indicated • Pop Y • Return from subroutines or interrupt • Push Y • Call subroutines or interrupt Sistemi Elettronici Programmabili

  25. RET RSP CALL subroutine Interrupt event PUSH Y POP Y IRET $0100 SP SP SP Y CC CC CC A A A X X X PCH PCH PCH SP SP PCL PCL PCL PCH PCH PCH PCH PCH SP $017F PCL PCL PCL PCL PCL Stack size and position is device dependent : • ST72254 : 128 bytes ($0100 to $017F) • ST72334 : 256 bytes ($0100 to $01FF) ST7 COREStack manipulation (2) Sistemi Elettronici Programmabili

  26. $00 PERIPHERALS HARDWARE REGISTERS $80 RAM 0 128 Bytes $0100 STACK 128 Bytes $0180 RESERVED $E000 ROM/EPROM 8KBytes $FFE0 INTERRUPTS & RESET VECTORS $FFFF ST7 COREThe memory space • THE MEMORY CAN BE MADE OF 6 DIFFERENT BLOCKS : • Peripherals hardware registerI/O Ports, TIM, ADC, WDG,SPI, I2C, EEPROM etc • Ram 0 : ram in first page • Stack : from 128 to 256 bytes (device dependent) • EEPROM Data (up to 256 bytes) • Program memory • Interrupt and Reset vectors Short Addressing Mode Location Sistemi Elettronici Programmabili

  27. ST7 IN-SITU PROGRAMINGRemote ISP • What is it for ? • To PROGRAM or REPROGRAM (flash devices) the Program Memory when the micro is soldered on the application board. • Main features: • Only 6 wires are used (including VDD & VSS). • Do not need double voltage on the application board. • Supported by the ST window eepromer tools. • Performances: • ~ 5 s to program 8Kbytes. Sistemi Elettronici Programmabili

  28. 1 Periphs ISPCLK ISPCLK ISPDATA ISPDATA RESET/ISPSEL VCC/VSS RESET/ISPSEL VCC/VSS 4 4 2 Software executed in RAM runs any applicative software with I/Os and peripherals access In-Situ Programming uses 6 wires only ST7 IN-SITU PROGRAMING (ISP)Remote mode I/Os Boot-ROM RAM RAM PROG MEMORY Software executed in RAM programs the prog memory PROG MEMORY Boot-ROM allows an executable software to be dowloaded in RAM through ISPCLK & ISPDATA Sistemi Elettronici Programmabili

  29. Memory & CPU registerSummary • How Many CPU registers belong to the ST7 Core? • Is it possible to place and read data in ROM (program memory)? • Is it possible to execute code located in RAM ? • Is the Stack handle automatically by the ST7 core ? Sistemi Elettronici Programmabili

  30. ST7 INTERRUPTSOverview • EXCEPT FOR THE SOFTWARE INTERRUPT (TRAP Instruction), ALLINTERRUPTS CAN BE MASKED BY SETTING THE I BITIN CC • WHEN AN INTERRUPT OCCURS : • The context is saved on the stack (CC, A, X, PC) • All other interrupts are masked (the I bit is set By H/W • The interrupt vector is loaded in the Program Counter • WHEN RETURN FROM INTERRUPT IS EXECUTED : • The original context is automatically restored (CC, A, X, PC) • Interrupts are enabled (I bit reset) • PRIORITY BETWEEN INTERRUPTS IS GIVEN BY THEINTERRUPT ADDRESS VECTOR Sistemi Elettronici Programmabili

  31. ST7 INTERRUPTSST72254 Interrupt mapping Sistemi Elettronici Programmabili

  32. ST7 INTERRUPTSPeripheral Int management Periph Status Register Interrupt flag set by H/W X X X X 1 X X X Periph Control Register Interrupt Enable bit set by S/W 1 X X X X X X X Condition Code Register Interrupt Mask bit set by S/W H N 1 1 1 0 Z C • Context switch takes 10 CPU clock cycles Interrupt generation Sistemi Elettronici Programmabili

  33. ST7 INTERRUPTPeripheral Int management • SOFTWARE EXAMPLE.Main...BSET Control_reg, #IT_enable ; Enable Periph interruptRIM ; Clear I bit in CC regis ... ; ie interrupt enabled.Int_routine...BRESStatus_reg, #IT_flag ; Avoid to process the; same interrupt foreverIRET ; Return from interrupt... Sistemi Elettronici Programmabili

  34. Interrupt Vectors: Number: S/W Priority * : Interrupt Reaction Time: Automatic register pushed: up 16 Vectors 16 levels hardwired 4 levels user configurable 1.250µs to 2.750 µs(end of the current instruction +10 cpu cycles) Program Counter, Accumulator, CC, X Software levels allows the ST7 nested interrupt process (only in the ST72511R & subsets) At least one Interrupt Vector per Peripheral ST7 Interrupt Summary Sistemi Elettronici Programmabili

  35. IT1 IT4 NMI IT2 IT0 IT3 NMI IT0 IT1 IT1 IT2 IT3 IT4 main main Concurrent Interrupt Management • An interrupt can not be interrupted by another one • Except by the NMI (Non Maskable Interrupt) Software Priority 3 3 3 3 Hardware Priority 3 RIM 3 3/0 Sistemi Elettronici Programmabili

  36. Interrupt Software Priority Level I1 I0 Level 0 (main) Low 1 0 Level 1 0 1 Level 2 0 0 Level 3 (=interrupt disable) High 1 1 Nested Interrupt • The 4 interrupt S/W levels are set thanks to the pair of bits I0, I1. • 1 pair of bits by interrupt vector stored in the ISPR registers • The pair of bits is copied in the CC register when the corresponding IT is activated (software level greater than the current one). Sistemi Elettronici Programmabili

  37. IT1 IT4 NMI IT2 IT0 IT3 Software Priority 3 NMI 3 IT0 2 IT1 IT1 1 IT2 IT2 Hardware Priority 3 IT3 RIM 3 IT4 IT4 main 3/0 main Nested Interrupt Management • An interrupt can be interrupted by: • The NMI (Non Maskable Interrupt) • An interrupt request having an highest software Priority Sistemi Elettronici Programmabili

  38. Interrupt Roadmap GP 42,44,56,64 pins GP 28,32 pins ST72104G1 ST72215G2 ST72216G1 ST72254G1/2 ST72314J2/4 ST72314N2/4 ST72334J2/4 ST72334N2/4 Concurent Interrupts Concurent Interrupts Auto 42,44,56,64 pins Dedicated Solutions ST72171K2 ST72411R1 ST72141K2 ST72532R4 ST72311R6/7/9 ST72512R4 ST72511R6/7/9 Nested Interrupts Concurent Interrupts Sistemi Elettronici Programmabili

  39. Interrupts Summary • How many interrupt vectors can be used in the ST7 ? • Are the software interrupt levels able to be modified during the application? • What are the instructions that enable & disable the Interrupts? Sistemi Elettronici Programmabili

  40. Multi oscillator (1) • ADVANCED ST7 CLOCK SYSTEM • Low frequency backup safety oscillator • Implemented on Reprogrammable devices only OSC1 OSC2 OSC1 OSC2 OSC1 OSC2 OSC1 OSC2 • EXTERNAL RC • EXTERNAL SOURCE • INTERNAL # 4Mhz • QUARTZ/CERAMIC Sistemi Elettronici Programmabili

  41. Frequency range 1 to 4 MHz 2 to 4 MHz 4 to 8 MHZ 8 to 16 MHz 1 to 14 MHz # 4 MHz # 250KHz 4 Crystal / Ceramic Oscillators Designed to reduce EMI & consumption Low speed Mid low speed Mid high speed High speed 1 External RC Oscillator 1 Internal RC Oscillator 1 Internal Safe Oscillator Oscillator selected by option byte Multi Oscillator (2) Sistemi Elettronici Programmabili

  42. Multi Oscillator (MO) Safe Oscillator Clock Filter Alternate Function Clock divider Values: 2,4,8,16,32 CORE & PERIPHERALS Main Clock Controller Clock Security System (CSS) OSC1 fOSC OSC2 Main Clock Controller (MCC) CLKOUT MCCSR Register Clock Divider fCPU Sistemi Elettronici Programmabili

  43. Clock Security System • Clock Filter Function • Safe Oscillator (# 250KHz) Main Oscillator Clock Internal ST7 Clock Main Oscillator Clock Safe Oscillator Clock Internal ST7 Clock CSSD bit is set by H/W if one of the safety function is activated and can generate a maskable interrupt request Sistemi Elettronici Programmabili

  44. ST7 CLOCK IN LOW POWER MODES • RUN MODES: Fcpu=Fosc/2 • Core & periph. running except if WAIT (Core stopped) selected • SLOW MODES: Division ratio from 4 to 32 by software • Core & periph. running except if WAIT (Core stopped) selected • ACTIVE HALT: Division ratio from 32000 to 400000 by software • Core & periph. stopped but periodic wake-up through interrupts • HALT MODE: Oscillator stopped • Core & periph. stopped Sistemi Elettronici Programmabili

  45. ST7 Clock System Roadmap GP 42,44,56,64 pins GP 28,32 pins ST72104G1 ST72215G2 ST72216G1 ST72254G1/2 ST72314J2/4 ST72314N2/4 ST72334J2/4 ST72334N2/4 Multi oscillator RC ext. 4Mhz int. 20% Safety oscillator SLOW: 4/8/16/32 ACTIVE HALT Multi oscillator RC ext. 4Mhz int. 20% Safety oscillator SLOW: 4/8/16/32 Auto 42,44,56,64 pins Dedicated Solutions ST72171K2 ST72411R1 ST72141K2 Idem as GP 28,32 pins Quartz/Ceramic/Ext.clock4Mhz min SLOW:4/8/16/32 ACTIVE HALT 7.16Mhz int / Ext.Clock SLOW:/32 ST72532R4 ST72311R6/7/9 ST72512R4 ST72511R6/7/9 Quartz/Ceramic/Ext.clock SLOW:4/8/16/32 Sistemi Elettronici Programmabili

  46. ST7 COREReset diagram (1) • EXTERNAL RESET USING RESET PIN • Purpose : allow to generate an external reset • Condition : reset pin pull low • POWER SUPPLY DEPENDEND RESET USING LVD • Purpose : ensure the MCU is in a known state whatever Vcc • Condition : internal reset when Vcc reaches Vcc min • WATCHDOG RESET USING THE WATCHDOG TIMER • Purpose : guarantee the safety in case of software trouble • Condition : internal reset when the WD register is not refreshed Sistemi Elettronici Programmabili

  47. 3 RESET SOURCES Watchdog Low Voltage Detection (LVD) External RESET pin COMPLETE RESET MANAGEMENT Flags on Reset sources Internal Reset externally issued to reset the whole application COMPLETE RESET SEQUENCE Phase with RESET pin grounded Internal Reset 4096 clock cycles Fetch Reset Vector From internal Watchdog Reset: Phase # 30µs From internal LVD Reset: 30µs<Phase<Low voltage duration From external RESET pin: 30µs<Phase<Ext RESET pulse width ST7 ENHANCED RESET SYSTEM Sistemi Elettronici Programmabili

  48. OSCILLATOR SIGNAL 30µs Delay ST7 COREReset diagram (3) VCC Internal Reset CK Ron COUNTER TO ST7 NRESET (ACTIVE LOW) RESET LVD RESET WATCHDOG RESET Sistemi Elettronici Programmabili

  49. Low consumption • RESET pin tied to GND • 3 Selectable levels • Activation Flag NEW ST7 LVD GENERATION Safe behaviour despite starting current sunk VCC supply VLVDr 250mV hysteresis VLVDf Min working VDD RESET Sistemi Elettronici Programmabili

  50. Safe 16Mhz area 3.8V Reset issued Freq. Absolute working window LVD med. LVD low LVD high 16Mhz Safe 16MHz area. 3.5V Reset issued 8Mhz Safe 8Mhz area Vsupply 3.0V 3.5V 4.0V 3 LVD LEVELS TO OPTIMIZE THE SAFE AREA Sistemi Elettronici Programmabili

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