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指導教授 : 林志明 級別 : 碩一 學生 : 呂致遠 民國 94 年 10 月 27 日

彰師大積體電路設計所 A 10b 125MS/s 40mW Pipelined ADC in 0.18 µ m CMOS 2005 IEEE International Solid-State Circuits Conference Masato Yoshioka, Masahiro Kudo, Kunihiko Gotoh, Yuu Watanabe Fujitsu Laboratories, Kawasaki, Japan. 指導教授 : 林志明 級別 : 碩一 學生 : 呂致遠 民國 94 年 10 月 27 日. Outline.

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指導教授 : 林志明 級別 : 碩一 學生 : 呂致遠 民國 94 年 10 月 27 日

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  1. 彰師大積體電路設計所A 10b 125MS/s 40mW Pipelined ADC in0.18µm CMOS2005 IEEE International Solid-State Circuits ConferenceMasato Yoshioka, Masahiro Kudo, Kunihiko Gotoh, Yuu WatanabeFujitsu Laboratories, Kawasaki, Japan 指導教授:林志明 級別:碩一 學生:呂致遠 民國94年10月27日

  2. Outline • introduction • ADC architecture • Proposed flip-around D/A converter (FADAC) • Operational amplifier • Summary of ADC performance • Chip photomicrograph • Measurements • Comparison • Conclusion • Applications • References

  3. ADC architecture

  4. Conventional pipelined ADC

  5. Conventional S/H and MDAC

  6. Circuit configuration of switched-capacitor amplifier

  7. Proposed flip-around D/A converter (FADAC).

  8. Schematic of amplifier.

  9. Summary of ADC performance

  10. Chip photomicrograph

  11. Measured INL and DNL

  12. SNDR versus input frequency

  13. Comparison to previous work

  14. ConclusionLow power consumption

  15. Applications • DTV • LCD • WLAN • xDSL

  16. References • [1] D. Miyazaki et al., “A 16mW 30MSample/s 10b Pipelined A/D Converter • Using Pseudo Differential Architecture,” ISSCC Dig. Tech. Papers, pp. 174- • 175, Feb., 2002. • [2] B.-M. Min et al., “A 69mW 10b 80MS/s Pipelined CMOS ADC,” ISSCC • Dig. Tech. Papers, pp. 324-325, Feb., 2003. • [3] K. Gotoh and O. Kobayashi, “3 States Logic Controlled CMOS Cyclic • A/D Converter,” Proc. CICC, pp. 366-369, May, 1986. • [4] W. Bright, “8b 75MSample/s 70mW Parallel Pipelined ADC • Incorporating Double Sampling,” ISSCC Dig. Tech. Papers, pp. 146-147, • Feb., 1998.

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