1 / 8

Generic Digitizer 10MHZ 16 bit 6U VME Board

Generic Digitizer 10MHZ 16 bit 6U VME Board. Futures. 12 channels, 16 bit at 6U VME Board DC- up to 10MSPS Operation Up to 500k sample per channel buffer Hardware & Software onboard data processing Smart triggering based on FPGA algorithm. 10MHz,16bit 3 channels ADC 4 CHIPS.

chapa
Download Presentation

Generic Digitizer 10MHZ 16 bit 6U VME Board

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Generic Digitizer 10MHZ 16 bit6U VME Board Generic Digitizer

  2. Futures • 12 channels, 16 bit at 6U VME Board • DC- up to 10MSPS Operation • Up to 500k sample per channel buffer • Hardware & Software onboard data processing • Smart triggering based on FPGA algorithm Generic Digitizer

  3. 10MHz,16bit 3 channels ADC 4 CHIPS Generic Digitizer VME BUS FPGA CYCLONE EP1C12240 State Machine Logic OR/AND NIOS Embedded Processor A n a l o g I n p u t s VME Drivers 4Mx32 SDRAM MT48LC4M32B2 JTAG 4 Mbit Serial Configuration Device EPCS4 EPCS4 Interface MAX7128 CLOCK IN 4 Mbit Serial FLASH Device EPCS4 CLOCK OUT GATE External Control TRIGGER TCLK SYNC IN SYNC OUT CRYSTAL 25MHz

  4. Digitizer Prototype LED s: Ready, VME, Gate, Trigger EXT Clock EXT Gate EXT Trigger SYNC TCLK VME DRIVER s HW Reset PreAMP s JTAG ADC s FPGA SDRAM 12 analog inputs 25MHz Crystal Mode Select SW Configuration Device HW Address Generic Digitizer

  5. AD9826 16-Bit Signal Processor • Features • 16-Bit 15 MSPS A/D Converter • 3-Channel 16-Bit Operation up to 15 MSPS • 1-Channel 16-Bit Operation up to 12.5 MSPS • Correlated Double Sampling • 1~6x Programmable Gain • ±300 mV Programmable Offset • Input Clamp Circuitry • Internal Voltage Reference • Multiplexed Byte-Wide Output • Optional Single Byte Output Mode • 3-Wire Serial Digital Interface The AD9826 is a complete analog signal processor. It features a 3-channel architecture designed to sample and condition the outputs of color CCD arrays. Each channel consists of an input clamp, Correlated Double Sampler (CDS), offset DAC, and Programmable Gain Amplifier (PGA), multiplexed to a high-performance 16-bit A/D converter. Generic Digitizer

  6. FPGA Design 3 channels x 4 = 12channels Data from ADC ADC Data Channels MUX Data MUX FIFO 512x16 Local BUS Arbiter & MUX SDRAM Interface SDRAM FIFO 512x16 Set ADC Mode, Gain, Offset FIFO 512x16 VME interface VME BUS ADC Serial Control interface Digitizer MODE Control TCLK Serial configuration Device Interface Gate Trigger Sync ADC CLOCK To EPCS4 Interface PLL Multiplier INT CLOCK 25MHz RF,53MHz Generic Digitizer

  7. LabView Interface Generic Digitizer

  8. STILL OPEN QUESTIONS • Channel to channel crosstalk is ~80dB at 10MHz from specification for AD9826. What is this ratio for a real board? And also, • What is a total ADC noise (3-9 LSB from spec) ? • What is a Integral and Differential Nonlinearity (16 and 0.5 LSB from spec)? Generic Digitizer

More Related