TYPE1 BOARD Type1 boards are compliant with 6U VME standard.

1. Type2 Ancillary DAQ . . . Type2 Type2 . . . Type1 Type1 Type1 Type1 Type1 Type1 16 16 An FPGA-based Trigger System for the MEG Experiment Experimental Apparatus Signal signature The MEG experiment searches for Lepton Flavour violating decays m+e+ + g with a sensitivity of 10-13 , two orders of magnitude better than current experimental limit set by MEGA collaboration. The experiment is operated at Paul Scherrer Institut laboratory (CH), where the most intense DC muon beam worldwide is capable of delivering up to 108μ/s. The experiment has been collecting data since September 12. Data taking is expected to last 3 years in order to achieve that sensitivity. • The MEG experiment combines different detection techniques, each developed to achieve unprecedented performances at such energies: • An 800l LXe calorimeter surveyed by 846 PMTs for photon detection; • A magnetic spectrometer made of 16 Drift Chambers (DC) coupled with a quasi-solenoidal magnetic field; • 30 Plastic Scintillator Bars (TC) for positron timing. Eg = 52.8 MeV Ee = 52.8 MeV DTge = 0 s qge = 180° Expected Resolutions THE TRIGGER SYSTEM TYPE2 BOARD It is a 9U VME board being used at the intermediate and top level of the trigger tree (see figure aside). It is capable of receiving up to 9 LVDS bus signals from as many lower level boards through 48 bit LVDS deserializer DS90CR482, the data transfer rate being 4.8 Gbit/s. Data link to the upper level is guaranteed by 2 DS90CR481 serializer. Transferred data are processed by Xilinx Virtex-IIpro FPGAs. All the algorithm logic is registered by a 100 MHz Clock signal distributed by a Roboclock CY7B994V, as in the case of Type1 boards. The so-called “Final Type2” collects all pieces of information from different detectors to look for an event signature; if found, the Stop signal to the DAQ is asserted. In a similar way, this boards waits for the Busy condition from all DAQ computers to be cleared and generates a Start signal as soon as it happens. These signals are embedded in a control bus including other information useful for DAQ software, such as the event counter and trigger type. TYPE1 BOARD Type1 boards are compliant with 6U VME standard. Each board receives 16 analog signals from experimental devices. These signals are digitized by means of 8 Flash ADC AD9218, with 10 bit resolution and 100 MHz sampling speed. A Xilinx FPGAs Virtex-IIpro receives digital data and operates first-level algorithms consisting in pedestal subtraction and calibration on all channels. The transmission of resulting data to second-level boards proceeds through LVDS serializers DS90CR481, the transfer rate being 4.8 Gbit/s. Clock reference signal, distributed by Ancillary boards, is multiplied by a factor 5 and distributed all over the board by a Roboclock CY7B994V. This chip provides an independent setting of skews with respect to the carrier signal, which is needed in order to synchronize FADC digitization, FPGA algorithm execution and data LDVS transmission. Requirements The Trigger System has to deal with huge detector occupancy. Such a harsh environment demands a very fast event selection. Another constraint to the trigger latency is associated with waveform digitizers, whose information is stored in 500 ns deep cyclic memories. Thus the trigger has to provide the Stop not later than 400 ns from the event occurrence. Such a system is also required to accomplish a powerful background rejection, so as to reduce the trigger rate below 10 Hz (livetime > 80%) while preserving the global efficiency > 95%. Finally it has to be flexible so as to accept other event types, along with normal running, needed for both detector calibration and monitoring. Hardware Implementation MEG Pisa group is responsible for the Trigger System. It is arranged in a multi-layer structure, as shown in the figure below: a first layer of so-called “Type1” boards to digitize signals and a second and third layer with “Type2” boards to collect Type1 data and operate selection algorithms. In addition, an Ancillary System was developed to ensure synchronous operation of the tree (data flux and algorithm execution). The logic is completely programmed into FPGAs and operates at 100 MHz frequency. The system consists in 40 Type1 boards, 6 Type2 and 4 Ancillary. SYNCRONIZATION Proper trigger operation is guaranteed provided algorithm execution on each board and data flow alongside the tree are synchronized. This is possible with a fine tuning of the skews of Roboclock CLK signals to both. We developed a monitoring tool for trigger synchronous operation which checks both data transmission and memory addressing. ANCILLARY BOARD This is a 9U VME board to distribute reference CLK and control signals (Start, Stop and Sync) to the entire Trigger System. The Ancillary System is arranged in a Master-Slave structure. The Master board is the one hosting the reference CLK oscillator, a SARONIX SEL3935 (19.44 MHz, jitter < 30 ps over 100.000 cycles) and receiving control signals from the “Final Type2” board. Those signals are fanned-out through MAXIM LVDS transmitters (maximum jitter < 13 ps, skew < 60 ps peak-to-peak over the 10 output) by 3 slave boards. These are equipped with programmable delay generators for the distribution of control signals. Algorithm Firmware Event selection utilizes observables like photon energy, photon-positron relative timing and direction. Intrinsic latency prevents us from using DC pieces of information to reconstruct positron momentum. Trigger algorithms uses signals coming from LXe calorimeter and TC PMTs. For instance, the weighted sum of the amplitude of LXe PMT signals provides an efficient estimator of gamma energy deposit in the calorimeter. Online Monitor of Synchronization Algorithms developed The system provides up to 32 different trigger types. Highest priority is assigned to MEG signal events; other related triggers, fulfilled by looser selection criteria, are acquired as well with proper pre-scaling in order to study trigger efficiencies. For instance, a dedicated trigger is associated with radiative muon decays, needed to cross-check the timing resolution of our detector. Lower priority triggers are also available for systematic studies on individual detectors. Trigger Rate and DAQ The MEG trigger rate at normal beam rate (3*107μ/s) turns out to be 5Hz as expected by Montecarlo simulations. Apart from trigger generation, this system is also conceived as a backup digitizing system for the experiment, with as good amplitude reconstruction capability as the main digitizers. Data recorded on WFD cyclic memories are read-out by on-line DAQ clusters by means of the 2EVME protocol. The total dead time of our DAQ system is approximately 40ms, corresponding ~83% of live time, in agreement with experimental requests. Example of a waveform digitized by the trigger system of a LXe PMT Trigger pre-scaling Lower priority trigger events have to be recorded during normal data taking for continuous detector calibration and efficiency monitoring. It is therefore desirable to program the fraction of each trigger type on a run-by-run basis. Pre-scaling factors can be defined at the beginning of each run so as to divide the trigger raw rates to the required values. The sum of the control trigger rates has to be lower than 1 Hz, in addition of 5 Hz of signal, to maintain livetime > 80%. The same for a TC PMT operating at B > 1T Trigger Counters The system also provides trigger rate counters for each type of selection algorithms used to control experiment normalization and efficiencies. LUCA GALLI, MEG EXPERIMENT INFN PISA