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CS 121 Digital Logic Design

Learn about gate-level minimization using the map method, simplification with product of sums, and handling don't care conditions in digital logic design.

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CS 121 Digital Logic Design

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  1. Chapter 3 CS 121Digital Logic Design Gate-Level Minimization

  2. Outline 3.1 Introduction 3.2 The Map Method 3.3 Four-Variable Map 3.5 Product of sums simplification 3.6 Don‘t Care Conditions 3.7 NAND and NOR Implementaion 3.8 Other Two-Level Implementaion 3.9 Exclusive-OR function

  3. 3.1 Introduction (1-1) • Gate-Level Minimization refers to the design task of finding an optimal gate-level implementation of the Boolean functions describing a digital circuit. • Notes about simplification of Boolean expression: • Minimum number of terms and literals in each term (minimum number of gates and inputs in the digram). • Reduce the complexity of the digital gates. • The simplest expression is not unique. • Simplification Methods: • Algebraic minimization  lack on specific rules. (section 2.4). • Karnaugh map or K-map.

  4. Outline 3.1 Introduction 3.2 The Map Method 3.3 Four-Variable Map 3.5 Product of sums simplification 3.6 Don‘t Care Conditions 3.7 NAND and NOR Implementaion 3.8 Other Two-Level Implementaion 3.9 Exclusive-OR function

  5. 3.2 The Map Method (1-12) • A Karnaugh map is a graphical tool for assisting in the general simplification procedure. • Combination of 2, 4, … adjacent squares • The relation is: Logic circuit ↔Boolean function ↔ Truth table ↔ K-map ↔ conical form ↔ satndrad form. • Conical form: ( sum of minterms , product of maxterms. • Standrad form: ( simplifier : sum of product , product of sum

  6. Y’ Y X’ X 3.2 The Map Method (2-12) Two-variable maps: • Number of sequares (minterms) is , where n is the number of variables. • So in tow-variable map there are 4 squares(minterms).

  7. 3.2 The Map Method (3-12) • Rules for K-map: • We can reduce functions by circling 1’s in the K-map • Each circle represents a mintermreduction • Following circling, we can deduce minimized and-or form. • Rules to consider • Every cell containing a 1 must be included at least once. • The largest possible “power of 2 rectangle” must be enclosed. • The 1’s must be enclosed in the smallest possible number of rectangles.

  8. 3.2 The Map Method (4-12) Two-Variable maps (cont.) Example 1: F(X,Y) = XY’ + XY From the map, we see that F (X,Y) = X. Note: There are implied 0s in other boxes. This can be justified using algebraic manipulations:F(X,Y) = XY’ + XY = X(Y’ +Y) = X.1 = X 1 1 X

  9. 1 1 1 3.2 The Map Method (5-12) Two-Variable maps (cont.) Example 2: G(x,y) = m1 + m2 + m3 Y G(x,y) = m1 + m2 + m3 = X’Y + XY’ + XY From the map, we can see that : G = X + Y X

  10. 1 1 x yF 0 0 1 0 1 1 1 0 0 1 1 0 3.2 The Map Method (6-12) Two-Variable maps (cont.) Example 3: F = Σ(0, 1) Using algebraic manipulations: F = Σ(0,1) = x’y + x’y’ = x’ (y+y’) = x’ X’

  11. 3.2 The Map Method (7-12) Three-variable maps: • 3 variables  8 squares ( minterms). • On a 3-variable K-Map: • One square represents a minterm with three variables • Two adjacent squares represent a product term with two variables • Four “adjacent” terms represent a product term with one variables • Eight “adjacent” terms is the function of all ones (logic 1).

  12. 3.2 The Map Method (8-12) Three-variable maps (cont.): Example 1: F(X,Y) = X’Y’Z’ + X’YZ’ + XY’Z’ + XYZ’ • using algebraic manipulations: F = X’Y’Z’ + X’YZ’ + XY’Z’ + XYZ’ = Z’ (X’Y’ + X’Y + XY’ + XY) = Z’ (X’ (Y’+Y) + X (Y’+Y)) = Z’ (X’+ X) = Z’ Y Z x 1 1 1 1

  13. 3.2 The Map Method (9-12) three-Variable maps (cont.) Example 2: F=AB’C’ +ABC +ABC +ABC + A’B’C + A’BC’ From the map, we see that F=A+BC +BC B C 11 01 00 10 A 1 1 0 1 1 1 1 1

  14. 3.2 The Map Method (10-12) three-Variable maps (cont.) Example 4 : F (x, y, z)= Σ(2, 3, 6, 7) Y using algebraic manipulations: F(x , y, z) = x’yz + xyz + x’yz’ + xyz’ = yz (x’ + x) + yz’ (x’ + x) = yz + yz’ = y (z + z’) = y y z 11 01 00 10 x 1 1 0 1 1 1

  15. 3.2 The Map Method (11-12) three-Variable maps (cont.) Example (3-1) , (3-2) :

  16. 3.2 The Map Method (12-12) three-Variable maps (cont.) Example (3-3) , (3-4) :

  17. Outline 3.1 Introduction 3.2 The Map Method 3.3 Four-Variable Map 3.5 Product of sums simplification 3.6 Don‘t Care Conditions 3.7 NAND and NOR Implementaion 3.8 Other Two-Level Implementaion 3.9 Exclusive-OR function

  18. 3.3 Four-Variables Map (1-9) • 4 variables  16 squares ( minterms). • On a 4-variable K-Map: • Two adjacent squares represent a term of three literals. • Four adjacent squares represent a term of two literals. • Eight adjacent squares represent a term of one literal. • Note:The larger the number of squares combined, the smaller the number of literals in the term.

  19. 3.3 Four-Variables Map (2-9) Flat Map Vs. Torus

  20. 3.3 Four-Variables Map (3-9) Example 1 (3-5) : F(w,x,y,z) = ∑ ( 0,1,2,4,5,6,8,9,12,13,14) y z 11 01 00 10 w x 1 1 00 1 W’YZ’ 1 1 1 01 Y’ XYZ’ 11 1 1 1 10 1 1 F = y‘ + w‘yz‘ + xyz‘

  21. 3.3 Four-Variables Map (4-9) Example 2 (3-6) : F = A’B’C’ + B’CD’ + A’BCD’ + AB’C’ C D B’C’ 11 01 00 10 A B 1 00 1 1 A’CD’ 01 1 11 1 1 1 10 B’D’ F = B‘D‘ + B‘C‘ + A‘CD‘

  22. 3.3 Four-Variables Map (5-9) Simplification using Prime Implicants • A Prime Implicantis a product term obtained by combining the maximum possible number of adjacent squares in the map . • If a minterm in a square is covered by only one prime implicant, that implicant is called Essential. • Prime Implicantsand Essential Prime Implicantscan be determined by inspection of a K-Map. • Notes: • Two adjacent 1’s form prime implicant, if they are not within a group of four adjacent squares. • Four adjacent 1’s form prime implicant, if they are not within a group of eight adjacent squares and so on.

  23. CD C B B D D B C 1 1 1 1 1 1 1 1 BD BD 1 1 B B 1 1 1 1 A A 1 1 1 1 1 1 1 1 A B D D AD Minterms covered by single prime implicant 3.3 Four-Variables Map (6-9) Simplification using Prime Implicants Example 1: F(A,B,C,D) = ∑ (0,2,3,5,7,8,9,10,11,13,15) ESSENTIAL Prime Implicants C

  24. 3.3 Four-Variables Map (7-9) Simplification using Prime Implicants Example 1: F(A,B,C,D) = ∑ (0,2,3,5,7,8,9,10,11,13,15) • Essential prim implicants:BD , B’D’ • Prime implicant: CD , B’C, AD , AB’. • The minterms that not cover by essential implicants are: m3, m9, m11. • The simplified expression is optained from the sum of the essential implicants and other prime implicants that may be needed to cover any remaining minterms. • So this function can be written with these ways: • F = BD + B’D’ + CD + AD • F = BD + B’D’ + CD + AB’ • F = BD + B’D’ + B’C + AD • F = BD + B’D’ + B’C + AB’

  25. Y X W Z 3.3 Four-Variables Map (8-9) Simplification using Prime Implicants Example 2: F(W,X,Y,Z) = ∑ (0,2,3,8,9,10,11,12,13,14,15) X’Y X’Z’ 1 1 1 Note: that all of these prime implicants are essential. 1 1 1 1 1 1 1 1 W

  26. Y X W Z 3.3 Four-Variables Map (9-9) Simplification using Prime Implicants Example 3: F(W,X,Y,Z) = ∑ (0,2,3,4,7,12,13,14,15) W’YZ W’X’Z’ W’X’Y • Essential: WX • Prime: XYZ , XY’Z’ , W’Y’Z’, W’YZ, W’X’Y , W’X’Z’ 1 1 1 W’Y’Z’ 1 1 XYZ 1 1 1 1 XY’Z’ WX

  27. Outline 3.1 Introduction 3.2 The Map Method 3.3 Four-Variable Map 3.5 Product of sums simplification 3.6 Don‘t Care Conditions 3.7 NAND and NOR Implementaion 3.8 Other Two-Level Implementaion 3.9 Exclusive-OR function

  28. 3.5 Producut-of-Sum simplification (1-3) • Mark with 1’s the minterms of F. • Mark with 0’sthe minterms of F’. • Circle 0’s to express F’. • Complement the result in step 3 to obtain a simplified F in product-of-sums form.

  29. C B A D 3.5 Producut-of-Sum simplification (2-3) Example 1: Simplify :F= ∑(0,1,2,5,8,9,10)in Product-of-Sums Form • F’ = AB + CD + BD’ • F = (F’)’ = (A’+B’) . (C’+D’) . (B’+D) CD 0 1 1 1 0 1 0 0 BD’ AB 0 0 0 0 1 1 0 1

  30. 3.5 Producut-of-Sum simplification (3-3) Example 2: Simplify: F(x, y, z) =(0, 2, 5,7)in Product-of-Sums Form X’Z’ y z 11 • F’ = XZ + X’Z’ • F = (F’)’ = (X’+Z’) + (X+Z) 01 00 10 x 0 0 0 0 0 1 XZ

  31. Outline 3.1 Introduction 3.2 The Map Method 3.3 Four-Variable Map 3.5 Product of sums simplification 3.6 Don‘t Care Conditions 3.7 NAND and NOR Implementaion 3.8 Other Two-Level Implementaion 3.9 Exclusive-OR function

  32. 3.6 Don't Cares Condition (1-4) • Sometimes a function table or map contains entries for which it is known: • The input values for the minterm will never occur, or • The output value for the minterm is not used. • Functions that have unspecified outputs for some input combinations are called incompletely specified functions. • In these cases, the output value is defined as a “don't care”( an “x” entry) assumed to be either 0 or 1. • The choice between 0 and 1 is depending on the way the incompletely specified function is simplied. • By placing “don't cares” in the function table or map, the cost of the logic circuit may be lowered.

  33. 3.6 Don't Cares Condition (2-4) • Example : • A logic function having the binary codes for the BCD digits as its inputs. Only the codes for 0 through 9 are used. • The six codes, 1010 through 1111 never occur, so the output values for these codes are “x” to represent “don’t cares.”

  34. Y Y X X W W Z Z 3.6 Don't Cares Condition (3-4) Example (3.9) : F(W,X,Y,Z) = ∑ (1,3,7,11,15) d(W,X,Y,Z) = ∑ (0,2,5) x 1 x x 1 x 1 1 x x 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 1 F = YZ + W’X’ F = YZ + W’Z

  35. Y X W Z 3.6 Don't Cares Condition (4-4) Example (3.9) : F(W,X,Y,Z) = ∑ (1,3,7,11,15) d(W,X,Y,Z) = ∑ (0,2,5) x 1 x 1 x 0 0 1 0 0 1 0 0 0 0 1 F’ = Z’ + WY’ F = Z ( W’ + Y)

  36. Outline 3.1 Introduction 3.2 The Map Method 3.3 Four-Variable Map 3.5 Product of sums simplification 3.6 Don‘t Care Conditions 3.7 NAND and NOR Implementaion 3.8 Other Two-Level Implementaion 3.9 Exclusive-OR function

  37. 3.7 NAND and NOR Implementation (1-15) • Digital circuits are frequently constructed with NAND or NOR gates rather than with AND and OR gates.

  38. 3.7 NAND and NOR Implementation (2-15) NAND Implementation • NAND gate: a universal gate. • Any digital system can be implemented with it.

  39. 3.7 NAND and NOR Implementation (3-15) NAND Implementation • To facilitate the conversion to NAND logic, there are alternative graphic symbol for it.

  40. 3.7 NAND and NOR Implementation (4-15) NAND Implementation Two-Level Implementation • Procedures (steps) of Implementation with two levels of NAND gates: • Express simplified function in sum of products form. • Draw a NAND gate for each product term that has at least two literals to constitute a group of first-level gates • Draw a single gate using AND-invert or invert-OR in the second level • A term with a single literal requires an inverter in the first level.

  41. 3.7 NAND and NOR Implementation (5-15) NAND Implementation Two-Level Implementation F = AB + CD = [(AB + CD)’]’ = [(AB)’*(CD)’]’

  42. 3.7 NAND and NOR Implementation (6-15) NAND Implementation Two-Level Implementation Example (3.10): F(X,Y,Z) = ∑ (1,2,3,4,5,7) X’Y F = XY’ + X’Y + Z y z 11 01 00 10 x 1 1 1 0 1 1 1 1 Z XY’

  43. 3.7 NAND and NOR Implementation (7-15) NAND Implementation Multilevel Implementation • Procedures (steps) of Implementation with multilevel of NAND gates: • Convert allAND gates to NAND gates with AND-invert graphic symbols • Convert all OR gates to NAND gates with invert-OR graphic symbols • Check all the bubbles in the diagrams. For a single bubble, invert an inverter (one-input NAND gate) or complement the input literal

  44. 3.7 NAND and NOR Implementation (8-15) NAND Implementation Multilevel Implementation EXAMPLE 1: F = A(CD + B) + BC’ B’

  45. 3.7 NAND and NOR Implementation (9-15) NAND Implementation Multilevel Implementation EXAMPLE 2: F = (AB’ + A’B).(C + D’) F C’ D

  46. 3.7 NAND and NOR Implementation (10-15) NOR Implementation • The NOR operation is the dual of the NAND operation. • The NOR gate is anothar universal gate to implement any Boolean function.

  47. 3.7 NAND and NOR Implementation (11-15) NOR Implementation • To facilitate the conversion to NOR logic, there are alternative graphic symbol for it.

  48. 3.7 NAND and NOR Implementation (12-15) NOR Implementation Two-Level Implementation • Procedures of Implementation with two levels of NOR gates: • Express simplified function in product of sums form. • Draw a NOR gate for each product term that has at least two literals to constitute a group of first-level gates • Draw a single gate using OR-invertor invert-ANDin the second level • A term with a single literal requires an inverter in the first level.

  49. 3.7 NAND and NOR Implementation (13-15) NOR Implementation Two-Level Implementation Example : F = (A+B).(C+D).E E

  50. 3.7 NAND and NOR Implementation (14-15) NOR Implementation Multilevel Implementation • Procedures of Implementation with multilevel of NOR gates: • Convert all OR gates to NOR gates with OR-invert graphic symbols • Convert all AND gates to NORgates with invert-AND graphic symbols • Check all the bubbles in the diagrams. For a single bubble, invert aninverter (one-input NAND gate) or complement the input literal

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