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2T1D Memory Cell with Voltage Gain Wing K. Luk, Robert H. Dennard

2T1D Memory Cell with Voltage Gain Wing K. Luk, Robert H. Dennard. Presented by: Madhulika Pannuri Department of Electrical Engineering VLSI SYSTEMS I. Size: 100 k bits. Power Supply: VDD = 1.2V and bit-line voltage = 0.6V. Cell size: 100kb

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2T1D Memory Cell with Voltage Gain Wing K. Luk, Robert H. Dennard

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  1. 2T1D Memory Cell with Voltage GainWing K. Luk, Robert H. Dennard Presented by: Madhulika Pannuri Department of Electrical Engineering VLSI SYSTEMS I

  2. Size: 100 k bits. • Power Supply: VDD = 1.2V and bit-line voltage = 0.6V. • Cell size: 100kb • Die size (using standard design rules) = 76F^2 ~ 2/3 SRAM cell. 120nm technology. • Word line material and routing width: • Cell capacitance: 2fF • Bit-line swing: 1.2V – 0.6V • Bit-line bias: 0.6V • Maximum refresh time: 70us @ room temperature. • Maximum cell / row: 256 cells / bitline. • Interfacing & clocking • External IO voltage

  3. 13. Burst Cycles supported: • 14. Error Correcting • 15. Number of banks • 16. • The 2T1D dynamic memory cell uses two transistor and a gate diode (D). • The gate diode is a MOS device consisting of a gate and a source. • When the gate to source voltage is above a threshold voltage, substantial amount of charge is stored in the inversion region. • When the gate to source voltage is below threshold, the charge stored is less. • The DRAM cells the stored voltage to turn on a transistor in the read-out path. Thus a non-destructive read. • Low wordline voltage to drive the write devices, resulting in small word line drivers compared to conventional DRAM.

  4. g) The voltage-sensitive capacitance characteristic of the gate diode and voltage boosting together provide 2T1D cell • Voltage amplification of the internal stored voltage. • Fast access • Short cycle. • Higher S/N ration • low voltage operation.

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