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Microarchitecture

Microarchitecture. Outline. Architecture vs. Microarchitecture Components MIPS Datapath. Architecture vs. Microarchitecture. Architecture What the CPU does Microarchitecture How the CPU does it. Architecture. What the CPU does CPU is a black box

charleigh-edwards
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Microarchitecture

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  1. Microarchitecture

  2. Outline • Architecture vs. Microarchitecture • Components • MIPS Datapath

  3. Architecture vs. Microarchitecture • Architecture • What the CPU does • Microarchitecture • How the CPU does it

  4. Architecture • What the CPU does • CPU is a black box • Only care about what goes in / comes out • Only need to know what instructions the CPU can execute • Instruction set architecture (ISA) • Realm of computer scientists • Don’t really care how it works under the hood

  5. Microarchitecture • How the CPU does it • Electrical mechanisms that allow CPU to execute instructions • Control paths, adder(s), multiplexors, memory units, etc. • Many possible microarchitectures for single architecture • Domain of computer and electrical engineers

  6. Architecture vs. Microarchitecture • Analogy: factory that produces auto parts

  7. Architecture vs. Microarchitecture • Architecture: don’t care about “how” factory runs, as long as the parts are good

  8. Architecture vs. Microarchitecture • Microarchitecture: care about “how” the factory runs

  9. Architecture vs. Microarchitecture • Microarchitecture: care about “how” the factory runs

  10. Architecture vs. Microarchitecture Intel Pentium IV AMD Bobcat x86 Architecture

  11. Outline • Architecture vs. Microarchitecture • Components • MIPS Datapath

  12. Von Neumann Model (basic structure of computer) MEMORY MDR MAR INPUT OUTPUT PROCESSING UNIT TEMP ALU CONTROL UNIT PC IR

  13. Components: Memory MEMORY MDR MAR INPUT OUTPUT PROCESSING UNIT TEMP ALU CONTROL UNIT PC IR

  14. Components: Memory MEMORY MDR MAR • 2k × m array of stored bits • E.g., 24 × 8 • Address • Unique (k-bit) identifier of location • Contents • m-bit value stored in location • Basic operations • STORE: write a value to memory location • LOAD: reada value from memory location

  15. Components: Memory MEMORY MDR MAR • Result of “LOAD 0010”?

  16. Components: Memory MEMORY MDR MAR • Result of “LOAD 0010”? 0110 1111

  17. Components: Memory MEMORY MDR MAR • How to read data to/from memory? • MAR: Memory Address Register • MDR: Memory Data Register • LOAD data from memory (address A) • Write the address (A)into MAR • Send a “read” signal to memory unit (memory unit will go get bytes, put into MDR) • Read the data from MDR

  18. Components: Memory MEMORY MDR MAR • How to read data to/from memory? • MAR: Memory Address Register • MDR: Memory Data Register • STORE data X in memory B • Write the data (X) into MDR • Write the address (B) into MAR • Send a “write” signal to memory (memory unit will do its thing to write X in location B)

  19. Components: Memory • What is controlling Memory? • The CONTROL UNIT of course!! • CONTROL UNIT sends signals • Instructs the other components • How does it know what signals (instructions) to send? MEMORY MDR MAR CONTROL UNIT PC IR

  20. Components MEMORY MDR MAR PROCESSING UNIT TEMP ALU CONTROL UNIT PC IR

  21. CONTROL UNIT Components: Control Unit PC IR • How does CONTROL UNIT know what to do? • Well, it doesn’t “know”.. • Control Unit follows command in the Instruction Register (IR) • Program Counter (PC) register holds memory address of the current instruction • What types of instructions do you think are available? • LOAD? STORE? ADD? SUBTRACT? OTHERS?

  22. CONTROL UNIT Components: Control Unit PC IR • Control Unit decodes instruction stored in IR • Sends signals to components based on decoded instruction • For example, perhaps the following instruction is in the IR

  23. CONTROL UNIT Components: Control Unit PC IR • In this simplified example, the instruction is decoded as: first two bits: 00 means LOAD last two bits: 01 refer to MDR next four bits: memory address to read from (0110)

  24. CONTROL UNIT Components: Control Unit PC IR • Based on this instruction, the Control Unit will activate the corresponding circuitry to signal the memoryunit to get data • This circuitry goes beyond the scope of this course • Consists of finite state machines of multiplexors, system clock, bus etc. first two bits: 00 means LOAD last two bits: 01 refer to MDR next four bits: memory address to read from (0110)

  25. CONTROL UNIT Components: Control Unit PC IR • If the instruction in the IR contains logic or arithmetic, the Processing Unit gets involved

  26. Components MEMORY MDR MAR PROCESSING UNIT TEMP ALU CONTROL UNIT PC IR

  27. Components: Processing Unit PROCESSING UNIT • Contains ALU • Arithmetic Logic Unit • Also contains temporary registers (TEMP) • Used for arithmetic operands • Used to store intermediate results of arithmetic operations • May also contain other functional units • Special purpose arithmetic: e.g., multiply, divide, etc. TEMP ALU

  28. Components: Processing Unit • How does Processing Unit know what to do? • Again, Control Unit sends electric signals that correspond to the appropriate instruction (e.g., ADD, SUBTRACT) PROCESSING UNIT TEMP ALU CONTROL UNIT PC IR

  29. Components: Processing Unit • Processing Unit getsdata from Memory Unit • Processing Unit putsdata into Memory Unit MEMORY MDR MAR PROCESSING UNIT TEMP ALU

  30. Components: Processing Unit ALU • ALU has its own inputs and output • Ais m-bit binary (input) • B is m-bit binary (input) • control tells ALU what to do (input) • E.g., add, subtract, divide, etc. • Usually control pins (high / low) • C is m-bit result (output) A B control PROCESSING UNIT C TEMP ALU

  31. Break Time!! ... wish I was there!!!

  32. Outline • Architecture vs. Microarchitecture • Components • MIPS Datapath

  33. MIPS Datapath • MIPS • Microprocessor without Interlocked Pipeline Stages • RISC Architecture: Reduced Instruction Set Computer • Microarchitecture of single-cycle MIPS processor…

  34. MIPS Single-Cycle Microarchitecture • We are going to “build” a single-cycle MIPS CPU

  35. MIPS Single-Cycle Microarchitecture • System clock • An oscillator that produces a square wave • E.g., 2.4 GHz processor- means 2.4 billion square waves per second • Components of CPU (memory, ALU, bus, etc.) synchronized to clock • Actions occur on “rising” or “falling” edge

  36. MIPS Single-Cycle Microarchitecture • Single-cycle CPU: • Executes an entire instruction in one clock cycle • Clock cycle time limited by slowest instruction one cycle

  37. MIPS Single-Cycle Microarchitecture • Overview of components used in diagram

  38. MIPS Single-Cycle Microarchitecture • PC: Program Counter • 32-bit register • Input (PC’): next instruction • Output (PC): current instruction • CLK: system clock

  39. MIPS Single-Cycle Microarchitecture • Instruction Memory • Single read port • Input: 32-bit instruction address(A) • Output: 32-bit data (i.e., instruction) (RD) • Note: this is an oversimplification that assumes the instruction memory is ROM (read only memory) • In reality, the instruction memory is writable; the OS can load new programs into memory

  40. MIPS Single-Cycle Microarchitecture • Register File (32 registers, 32-bits each) • Inputs: • A1: 5-bit address specifying a register (to read) • A2: 5-bit address specifying a register (to read) • A3: 5-bit address specifying a register (to write) • WD3: 32-bit data to write to register • CLK: system clock • WE3: write enable (single bit) • Outputs: • RD1: 32-bit register value specified by 5-bit address A1 • RD2: 32-bit register value specified by 5-bit address A2

  41. MIPS Single-Cycle Microarchitecture • Data Memory • If WE (Write Enable) is 1, • Writes data WD into address A on rising edge of clock (CLK) • If WE is 0, • Reads address A onto RD on rising edge of clock (CLK)

  42. MIPS Single-Cycle Microarchitecture • Start by building the datapath • First step, connect PC to Instruction Memory • PC register contains address of instruction • Instruction Memoryfetchesinstruction (instr) from memory PC instr

  43. MIPS Single-Cycle Microarchitecture

  44. MIPS Single-Cycle Microarchitecture • Next step, things start to get more complicated • The instruction (instr) gets decoded by the control unit • The appropriates pins (e.g., write enable) get set • The 5-bit register addresses (in the Register File) get specified • (Things get “set up” for execution)

  45. MIPS Single-Cycle Microarchitecture

  46. MIPS Single-Cycle Microarchitecture • Next, execution occurs (based on instruction)

  47. MIPS Single-Cycle Microarchitecture • Then, the result of execution interacts with memory (somehow)

  48. MIPS Single-Cycle Microarchitecture • The process then starts over…

  49. MIPS Single-Cycle Microarchitecture • Let’s look at the datapath for a concrete example • MIPS assembly instruction lw (stands for “Load Word”) • lw loads 32-bits of data from a memory address to a register • Please keep in mind that we will NOT use MIPS assembly, we will use x86 • This is for demonstration purposes only, x86 datapath is more complex

  50. MIPS Single-Cycle Microarchitecture: lw example • Step 1: fetch the instruction

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