Proposal : 2.5 Gbps Radiation Tolerant Serializer Design for the CBM–DAQ in 180 nm CMOS process

Proposal: 2.5 Gbps Radiation Tolerant Serializer Design for the CBM–DAQ in 180 nm CMOS process Pradeep Banerjee, Dr. T. K. Bhattacharyya, E & ECE Dept., Indian Institute of Technology, Kharagpur 15th CBM Collaboration Meeting, GSI 12th - 16th April 2010

Outline • New Proposal for a separate Data Aggregation chip • Architecture and Circuit Options for the High speed Serializer • Some aspects of Radiation Tolerant design in deep submicron CMOS • Activities at the RF IC group at AVLSI Lab, IIT KGP 15th CBM Collaboration Meeting

The CBM Generic Read-out Chain DAQchain Detector Sub-System FLES Front-EndBoard Detector Read-OutController Active BufferBoard Data CombinerBoard First LevelEvent Selector FEB ROC DCB ABB FLES Data &Control Data Control Data DCS Sync TNet FEE DAQInterface Local Pre-Processing DigitizationCustom ASIC DAQFLESInterface FPGA Coprocessor Buffering SystemSynchronization Event Selection CPU Farm Slide Info: Walter F.J. Müller, GSI 15th CBM Collaboration Meeting 3

STS Data Rates – Aggregation Very few chip in inner region have hit rate > 32 MHz > 90% of chips have hit rates in 2...16 MHz range AMPLE SCOPE FOR DATA AGGREGATION 31.25 MHz hit rate  2.5 Gbps Au+Au @ 25 AGev107 evt/sec Hit rate per chip Statistics Slide Data from: Walter F.J. Müller, GSI 15th CBM Collaboration Meeting 4

STS FEB Type and Link Distribution • 38 chips exceed 2.0 Gbps: 29 with 2.0 … 2.4; 9 with 2.4 … 3.2; • # of FEBs and type distributions varies for stations Slide Data from: Walter F.J. Müller, GSI 15th CBM Collaboration Meeting 5

Data Aggregation on separate chip - Communication hub • Motivation: • Data Aggregation: In most cases 2,4, or 8 CBM-XYTER chips (FEBa2, FEBa4, FEBa8, resp.) can be aggregated to fill a 2.5 Gbps link • Increase the bandwidth available per link • Reduce the number of Optical Links • Schemes: • Embedded (aggregation integrated in CBM-XYTER) • Data aggregation and Traffic Managementwith a separate Communication Controller Asic  • Clock Distribution • Slow control traffic • Data Readout traffic Communication ‘hub’ 15th CBM Collaboration Meeting 6

Xyter #1 A peep into some feasible ‘Hub’ ASIC Requirements • Capacity for data aggregation from several Readout-ASICs into a single output link • 1 ‘hub’ ASIC may contain 6 high speed Serializers : 6 Tx for data  15 Gbps serviceable data bandwidth • 1 Rx – 1 Tx channel for clock, sync, control • 250 MHz sys clock as Transmit clk  500 Mbps (DDR LVDS) input interface • 5-8 LVDS o/p links (each 500 Mbps) per chip  • FEBa8 case : 1 LVDS link per chip: combinedata of 6 FEBs (48 LVDS links) per Hub • FEBa1 case : All 6 LVDS links (single chip) per Serializer • Cross-Connect Topology: Dynamic load balancing b/w the 6 output links desirable FEB sys_clk HUB Asic Serializer #1 Six 2.5 Gbps o/p links 5-8 LVDS links (500 Mbps) per chip Serializer #2 Xyter #2 Detector i/f #6 #8 PLL Clk Gen clock, sync, control i/f 15th CBM Collaboration Meeting ‘Hub’ Idea: Walter F.J. Müller, GSI 7

High Speed Serializer Core • Design of the following functional blocks: • High speed Serializer (2.5 Gbps) • PLL and Clock generator • Output Driving Logic (impedance matched) • Technology: • CMOS process of interest: UMC 180 nm (Available through Europractice) • Beneficial Features for Radiation tolerant design: • Retrograde wells • Shallow Trench Isolation 15th CBM Collaboration Meeting 8

Serializer “Primer” • Parallel-load Shift register: • Cascade of flip-flops and 2-to-1 multiplexers • Operation speed is limited by: • Clock to Q delay • Mux delay • Flip-flop setup time • Maximum frequency: • 1/(tcq + tmux + tsetup) • Static Flip-Flops: • Operation @ 2.5 Gbps  T = 400 ps • Speed constraint • Can we use Dynamic Flip-Flops? • No, they are sensitive to SEUs • Other high speed options: • Current Mode Logic 15th CBM Collaboration Meeting 9

2.5 Gbps Serializer ASIC block diagram BIST gen TXP D(0:9) 2.5 Gbps 50 ohm driver Word Mux 10 bit Serializer d(0:9) TXN 250 MHz Tx Clk 1.25 GHz load 2.5 GHz PLL Ref 2.5 GHz Clock Generator PLL Not shown: FIFOs, Arbitration logic (token ring), 8B/10B Encoders 15th CBM Collaboration Meeting 10

Multiple Serializer Core: Design Challenges • Jitter-free Clock signalMinimize noise contribution of VCO (Total serial o/p jitter < 120 ps for BER ~ 10-12) • Switching noise generated by digital logic in ASIC • Constantphase relationship b/w VCO and Sys clock (400 ps bit time) • MultipleSerializer cores per chip: • Power efficiency, ASIC footprint • Sharinga single frequency multiplier among several Serializer cores in the same ASIC : • Distributing multi-gigahertz clocks over an extended distance consumes lot of power • Signal integrity issues  percentage of area saved as a function of the number of cores for a PLL that is half the size of a Serializer core saturates beyond 4 • Careful planning on circuit layout  buffering high speed clock in cascade actually worsens jitter performance • De-Serializer: CDR complexity 15th CBM Collaboration Meeting 11

Serializer – Dual phase Architecture 15th CBM Collaboration Meeting 12

Serializer – Dual phase Architecture … • Word-clock = (1/10) * VCO Clock ( = 2.5 GHz) • Bit-clock = (1/2) * VCO Clock • Multiphase Clock generation for further reduction of clocking speed • Issues: Duty cycle distortion jitter 15th CBM Collaboration Meeting 13

Background – Rad-hard design • Ionizing radiation effects on CMOS ICs: • Total Ionizing Dose (TID) Effects • Issues : threshold-voltage shifts, mobility degradation, and isolation related leakage • Remedy : “Radiation tolerant Layout techniques” – Systematic use of Annular Symmetric Enclosed Layout Transistors (ELT) and p+ guard rings between the n+ diffusions • Single Event Effects (SEE) • Variants: • Non-Destructive : Single Event Upset (SEU), Single Event Transient (DSET) • Destructive : Single Event Latch-Up (SEL) • Issues: • SEU : Depending on the LET, if parasitic charge > node critical charge, a logical switch may occur (bit flip) • DSET : Error rate depends linearly on Clock frequency (glitch) • SEL : Parasitic thyristor structure leading to latch-up • Remedy: • SEU/DSET: Temporal Sampling – Triple Modular Redundancy (TMR), Error Detection and Correction (EDAC);Add Capacitance to sensitive nodes to increase ‘critical charge’ • SEL : Radiation tolerant Layout techniques and usage of p+ guard rings 15th CBM Collaboration Meeting 14

Background cont ... Rad-hard design • Observations/Experience in CBM Radiation Environment: • TID : • MUCH plane 1 (at 130 cm) : deposited energy (rad/CBM-yr) • at perimeter: ~30krad/yr, in center: ~500krad/yr • Not necessary to have all transistors with ELT layout • SEL: • Not seen as an issue in tests so far in deep submicron CMOS • SEU/SET: • MUCH plane 1 (at 130 cm) : fluence hadron E>20 MeV (/cm2/CBM-yr) • at perimeter: ~2·105 h/cm2/s, at center: ~2·106 h/cm2/s • Hadrons flux VERY Significant for SEUs 15th CBM Collaboration Meeting 15

Approach: Work Plan • Freeze System level/Interface Specs • Design an appropriate architecture for the High speed Serializer core • Design and Implementation of the Peripheral cores in UMC 180μm process: • PLL • Clock generator • 50 ohm output Impedance driver • Characterization of UMC 0.18μm CMOS process concerning the vulnerability against SEU / SETs • Testing : • Functionality/Performance : Design of different Testing/Digital blocks: • Pseudo Random Sequence generator (PRSG) • 8B/10B encoder, FIFOs • FPGA devices to program the Serializer Test Configuration • generation of Test data patterns • monitor PLL’s locking state, etc. • Radiation Tolerance 15th CBM Collaboration Meeting 16

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Resources Available at AVLSI Lab, IIT KGP 15th CBM Collaboration Meeting 21

THANK YOU FOR YOUR ATTENTION 15th CBM Collaboration Meeting 22

Proposal : 2.5 Gbps Radiation Tolerant Serializer Design for the CBM–DAQ in 180 nm CMOS process