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Multilevel Ring Tuning for Post-Silicon Active Clock Deskewing

Explore adaptive clock skew tuning methods over PVT variations for efficient post-silicon tuning. Learn about Quadrantal Ring Tuning, DLL, Up/Down Detector, and more techniques for clock deskewing. Enhance clock stability and accuracy in sub-micron technologies.

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Multilevel Ring Tuning for Post-Silicon Active Clock Deskewing

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  1. Multilevel Ring Tuning for Post-Silicon Active Clock Deskewing Fariborz Dadnam Professor Lei He

  2. PVT Variations • Process Variations • Inter-die • Die-to-die variations • Intra-die • Within-die variations • Significant impact on sub-micron technologies • Voltage Variations • Temperature Variations Multilevel Ring Tuning for Post-Silicon Active Clock Deskewing

  3. Silicon Tuning Pre-Silicon Post-Silicon After fabrication ATE feedback Adaptive circuits • Design/layout phase • Predictable variations Our Focus: adaptive post-silicon clock skew tuning Clock skew: spatial variation Clock jitter: temporal variation Multilevel Ring Tuning for Post-Silicon Active Clock Deskewing

  4. Various PST Approaches • Dynamically adjust clock skew • Adjustable delay buffers (ADB) and Phase detectors (PD) • Adjust the Vth of clock buffer transistors • Hot carrier injection (HCI) • Path-based learning • Employing statistical timing tools to develop regression simulator • … PST: post-silicon tuning Multilevel Ring Tuning for Post-Silicon Active Clock Deskewing

  5. Different Techniques’ Objective • Eliminating the number of PST components • Area, power, cost • Optimizing algorithms • Accuracy, speed • Organizing PST components • Less components, optimization Multilevel Ring Tuning for Post-Silicon Active Clock Deskewing

  6. Quadrantal Ring Tuning (QRT)An Active Post-Silicon Tuning Method for Clock Deskewing over PVT Variations From the paper by J. G. Mueller and R. A. Saleh Multilevel Ring Tuning for Post-Silicon Active Clock Deskewing

  7. Delay-Locked Loop (DLL) A single DLL unit Multilevel Ring Tuning for Post-Silicon Active Clock Deskewing

  8. Up/Down Detector (UDD) • Measures the skew between the reference clock and the leaf (clk L and clk R) • Concerns, • Receiving accurate clock signals • Setting up/down thresholds precisely • In the locked state, no tuning adjustments will be made • UP and DOWN can never both be high simultaneously Multilevel Ring Tuning for Post-Silicon Active Clock Deskewing

  9. Thermometer Code Generator and Tunable Buffer (TCG) (TB) Clock buffer/inverter to provide selectable delay Spans whole tuning range • Converts the control signals (UP/DOWN) from UDD to control word (e.g. 3-bit) for TB • Placed next to TB • Two clock-cycle wide • One tuning step at a time Multilevel Ring Tuning for Post-Silicon Active Clock Deskewing

  10. Stable DLL over PVT Variations • Distribution across entire chip  subject to various intra-die PVT variations • Step size (ss) • Skew threshold (Sth) ss = tuning_range/(#bits - 1) Sth= 1.5 × ss • To ensure, • DLL locking • Loop stability Multilevel Ring Tuning for Post-Silicon Active Clock Deskewing

  11. QRT Architecture Tuning Zones Clock Buffers Tunable Buffers • Tuning Zones Selection • Simpler control of fewer, large tuning zones • vs. • Higher precision/accuracy of more, small tuning zones • UDDs Location • Minimize routing • and • Maximize skew measurement accuracy   Multilevel Ring Tuning for Post-Silicon Active Clock Deskewing

  12. Single-Level QRT Feedback (or tuned) clock of one zone becomes the reference clock of its counter-clockwise neighboring zone! Multilevel Ring Tuning for Post-Silicon Active Clock Deskewing

  13. Multi-Level QRT • Total of sixteen additional UDDs, TCGs, and TBs • Tuning range of 50ps for clock level-2 vs. 20ps for clock level-3 • The sub-skews within each quadrant will be reduced, and therefore, the overall chip’s clock skew will also be reduced Multilevel Ring Tuning for Post-Silicon Active Clock Deskewing

  14. PVT Variation Modeling PVT Variations • Spatial variations (cone function) z2 = (x – a)2 + (y – b)2 in MATLAB [z(x, y) cone function] • Random variations (Monte Carlo simulation) gauss() function in HSPICE [Gaussian RV(µ, σ)] (a, b) Multilevel Ring Tuning for Post-Silicon Active Clock Deskewing

  15. Simulation Variables • Transistors’ • Channel width • Leakage • Capacitors • Resistors • Wires’ • Length • Resistance per unit length • Capacitance per unit length Multilevel Ring Tuning for Post-Silicon Active Clock Deskewing

  16. Total PVT Variation P = Pnom + ∆Pinter + ∆Pspatial(xi, yi) + ∆Prandom,i Pnomnominal value ∆Pinterinter-die variation ∆Pspatialintra-die variation, function of location (x, y) ∆Prandomsome amount of random variation Multilevel Ring Tuning for Post-Silicon Active Clock Deskewing

  17. Result: Single Level Multilevel Ring Tuning for Post-Silicon Active Clock Deskewing

  18. Result: PVT Variations (A) (B) (C) (D) (E) (F) Multilevel Ring Tuning for Post-Silicon Active Clock Deskewing

  19. Result: Overall Comparison No tuning QRT level-2 only QRT level-2 & 3 Multilevel Ring Tuning for Post-Silicon Active Clock Deskewing

  20. References [1] X. Li, B. Taylor, Y. Chien and L. T. Pileggi, "Adaptive Post-Silicon Tuning for Analog Circuits: Concept, Analysis and Optimization," IEEE, pp. 450-457, 2007. [2] Z. Lak and N. Nicolici, "A New Algorithm for Post-Silicon Clock Measurement and Tuning," IEEE, pp. 53-59, 2011. [3] J. G. Mueller and R. A. Saleh, "Autonomous, Multilevel Ring Tuning Scheme for Post-Silicon Active Clock Deskewing Over Intra-Die Variations," IEEE, vol. 9, no. 6, pp. 973-986, June 2011. [4] S. H. Kulkarni, D. Sylvester and D. Blaauw, "A Statistical Framework for Post-Silicon Tuning through Body Bias Clustering," ICCAD, pp. 39-46, November 2006. [5] J.-L. Tsai, L. Zhang and C. C.-P. Chen, "Statistical Timing Analysis Driven Post-Silicon-Tunable Clock-Tree Synthesis," IEEE, pp. 574-580, 2005. [6] J. G. Mueller and R. Saleh, "A Tunable Clock Buffer for Intra-die PVT Compensation in Single-Edge Clock (SEC) Distribution Networks," IEEE, pp. 572-577, 2088. [7] S. Naffziger, B. Stackhouse, T. Grutkowski, D. Josephson, J. Desai, E. Alon and M. Horowitz, "The Implementation of a 2-Core, Multi-Threaded Itanium Family Processor," IEEE, vol. 41, no. 1, pp. 197-209, January 2006. [8] Y. Pu, X. Zhang, K. Ikeuchi, A. Muramatsu, A. Kawasumi, M. Takamiya, M. Nomura, H. Shinohara and T. Sakurai, "Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits," IEEE, pp. 294-298, 2011. [9] M. Y. Kao, K.-T. Tsai and S.-C. Chang, "A Robust Architecture for Post-Silicon Skew Tuning," IEEE, pp. 774-778, 2011. Multilevel Ring Tuning for Post-Silicon Active Clock Deskewing

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