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Pre Silicon to Post Silicon Verification

Pre Silicon to Post Silicon Verification. Ran Snir Verification Team Manager CEVA, Inc. Verification Leader Course 2005. Outline. Introduction Problems Reuse questions Coverage Post-silicon verification DBG Verifier. Introduction. Traditional Verification Flow

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Pre Silicon to Post Silicon Verification

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  1. Pre Silicon to Post Silicon Verification Ran Snir Verification Team Manager CEVA, Inc. Verification Leader Course 2005

  2. Outline • Introduction • Problems • Reuse questions • Coverage • Post-silicon verification • DBG Verifier

  3. Introduction • Traditional Verification Flow • Reach 100% code and functional coverage • Equivalent checking between GDSII (or FPGA net-list) and RTL • Tape-Out • Between tape-out and chip arrival develop verification environment for the Chip (fundamental verification) • Basic silicon validation • Run software kernel or complete software on post-silicon

  4. Problems • Design complexity increase • Complex verification components (amount of data transfer is huge) • Simulator performance increase but simulation time remain the same (1-20KHz) • FPGA capability and performance increase, however debug and integration with verification language remain poor • Hardware accelerator are very expensive • Running on post silicon is faster… • Debug on post silicon is slower…

  5. Reuse Questions • Do we need the same verification on pre-silicon and post-silicon? • Do we need random verification on post-silicon? • Which parts of the verification environment are worth reusing in post silicon? • How to use high-level description language for post-silicon/FPGA validation?

  6. Coverage • When can we tape-out (on what coverage percentage)? • Functional coverage • Code coverage • How to measure coverage on a FPGA/silicon? • How to use “real” software as part of the test-bench? • Are 100% functional coverage + equivalence checking enough?

  7. Post-Silicon Verification • How can we detect post-silicon bugs that can’t be detected on pre-silicon?

  8. DBGVerifier Introduction • The DBGVerifier aim is to verify a connection between a debugger session and customer’s SoC • The DBGVerifier can verify such a connection in a RTL level or FPGA level. The Idea is to verify the CHIP emulation in advance (pre-silicon) Chip/ FPGA/ RTL DBGVerifier

  9. DBG Verifier • The Ceva DBG Verifier is a Verilog model of the Ceva JTAG Box • The RTL environment is: • Unix based system • Debugger software is connected via PLI to DBG Verifier • DBG Verifer is connected to RTL • The FPGA/Silicon environment is: • PC based system • Debugger software is connected via PLI to JTAGBox • JTAGBox is located on board, connected to FPGA or silicon

  10. PLI interface PLI interface Interface between the debugger software and the Verilog model pp_emul Translates the debugger signals to EPP protocol Jtag interface clock _gen Generate system clock The top RTL module of the jtag box. System Architecture cevaX_DBG_verifier Debugger cevaX1620 clock _ gen PP2JTAG_TOP tdo tdi p pp ocem p tck _ interface e rtck m u l tms core

  11. Thank you

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