Computer Architecture

1. Computer Architecture An exploration of a few simple ideas P Joy Prabhakaran

2. 1. Fundamentally….Computing with Switches

3. Binary numbers Decimal numbers • Base 10 • 10 symbols: 0 to 9 • 576 = 5 x 102 + 7 x 101 + 6 x 100 Binary numbers • Base 2 • 2 symbols: 0 & 1 • 101 = 1 x 22 + 0 x 21 + 1 x 20 = ? In decimal

4. Compute: How? • Logic NOT, OR, AND, XOR • Numeric Comparison =, >, < • Arithmetic ADD, SUB, MULT, DIV Can all these be built using the switches shown here? Many of the ideas here can be from Shannon’s work referred to at: http://en.wikipedia.org/wiki/A_Symbolic_Analysis_of_Relay_and_Switching_Circuits

5. The NOT gate A few notations concerning the switches: 5V, 1, ON, TRUE are all used in a near synonymous manner. The switch is “pressed” when the Input is 1. If the connection to 5V is not present, the output is at 0. Also referred to as OFF or FALSE at times. With that out of the way let us explore what the NOT logic is and if we can implement it using these switches.

6. AND The “AND” logic How can this be built using our switches?

7. OR The “OR” logic How can this be built using our switches?

8. XOR The “XOR” logic How can this be built using our switches?

9. Gates and the symbols to denote them

10. Checking for equality What does the following do? O/P =

11. Addition: One bit half adder Two inputs (A, B) and two outputs ( S, Cout) Addition operation A one bit half adder: What is the truth table for S and Cout? What is the logic for S and Cout?

12. One bit full adder Three inputs (A, B, C) and two outputs (S, Cout) Addition operation A one bit full adder: The truth table for S and Cout … and the logic S and Cout? • S is true if only one input is true or if all three are true. • Cout is true if any two inputs are true.

13. Other concepts that can be realized using switches • Storage elements (latches, flip flops) • Edge triggered devices: the concept of clocking • Counters • Registers (serial & parallel load) • Decoders

14. Store: A few examples of data storage • Mechanical • Electrical • Magnetic • Optical

15. Store: A few examples of data storage

16. A conceptual exploration of addressable and programmable storage with no moving parts What is O/P in relation with A1? Assuming only one of A1 and A2 can be 1 at any time, what is the relationship between A1 and A2 in the two schematics on the right Any ideas on how all this could lead to a memory device?

17. ...conceptual exploration of memory Discuss how the schematic can become the basic idea behind devices like RAMs, EPROMs, EEPROMs etc with Ai becoming the addressing mechanism

18. 2. Our wishes, its commandsThe Stored program

19. Von Neumann Architecture: A stored program architecture • A stored-program digital computer is one that keeps its program instructions, as well as its data, in read-write, random-access memory (RAM). • The earliest computers were not so much "programmed" as they were "designed". • "Reprogramming", when it was possible at all, was a laborious process, starting with flowcharts and paper notes, followed by detailed engineering designs, and then the often-arduous process of physically rewiring and rebuilding the machine. • It could take three weeks to set up a program on ENIAC (1940s) and get it working. --- wikipedia

20. Von Neumann Architecture Von Neumann architecture is a design for an electronic digital computer. It consists of: • A processing unit containing • an arithmetic logic unit • processor registers • A control unit containing • an instruction register • program counter • A memory to store both data and instructions, • External storage • Input and output mechanisms

21. Von Neumann Architecture Source: https://en.wikipedia.org/wiki/Von_Neumann_architecture

23. Getting everything talk to each otherThe Bus Interconnection Scheme William Stallings: Computer Organization and Architecture

24. Bus Interconnection: An ISA connector

25. A more detailed view of the architecture

26. What happens on the bus(es) during a typical read cycle S0, S1 are status signal and output from the processor. http://www.zseries.in/embedded%20lab/8085%20microprocessor/timing%20diagram.php#.V6X_EoN97IU

27. Doing what the program ordersInstruction by Instruction

28. Floating Point - IEEE 754 32 bit format • +/- .significand x 2exponent • Misnomer • Point is actually fixed between sign bit and body of mantissa • Exponent indicates place value (point position) • Exponent is represented as what is called biased representation, i.e. value + 127 • Significand used to be called mantissa but that nomenclature is considered obsolete.

29. Expressible Numbers

30. 3. The multi-billion transistor gorillaThe CPU

31. Exploring the CPU

32. All that the processor does • Fetch instruction • The processor reads an instruction from memory (register, cache, main memory) • Interpret instruction • The instruction is decoded to determine what action is required • Fetch data • The execution of an instruction may require reading data from memory or an I/O module • Process data • The execution of an instruction may require performing some arithmetic or logical operation on data • Write data • The results of an execution may require writing data to memory or an I/O module In order to do these things the processor needs to store some data temporarily and therefore needs a small internal memory.

33. The role of the registers Within the processor there is a set of registers that function as a level of memory above main memory and cache in the hierarchy. The registers in the processor perform two roles: Control and Status Registers User-Visible Registers Enable the machine or assembly language programmer to minimize main memory references by optimizing use of registers Used by the control unit to control the operation of the processor and by privileged operating system programs to control the execution of programs

34. Control and Status Registers The registers used in instruction execution • Program counter (PC) • Contains the address of an instruction to be fetched • Instruction register (IR) • Contains the instruction most recently fetched • Memory address register (MAR) • Contains the address of a location in memory • Memory buffer register (MBR) • Contains a word of data to be written to memory or the word most recently read Not all processors have internal registers designated as MAR and MBR, but some equivalent buffering mechanism is needed whereby the bits to be transferred to the system bus are staged and the bits to be read from the data bus are temporarily stored.

35. The processor at work Data Flow, (Instruction) Fetch Cycle

36. Let us do a fly-by of the Control Unit • In addition to the IR, the control unit takes different flags, clock and control signals from the control bus as inputs. • The control signals from the control unit would be connected to the small circles on the arrows.

37. Few Data Paths and Control Signals Fetch t1: MAR <- (PC) t2: MBR <- (memory) PC <- (PC) +1 t3: IR <- (MBR) (tx = time unit/clock cycle) Note: Discuss hardwired vs. micro-programmed architecture.

38. Pipelining – a case of clever engineering Hazards – because nothing comes easy Fetch instruction (FI) Decode instruction (DI) Fetch operands (FO) Execute instruction (EI) Write operand (WO) Assuming that main memory has a single port and ignoring the caches, an operand read to or write from memory cannot be performed in parallel with an instruction fetch.

39. 4. The team that deliversThe Motherboard

40. The motherboard and the stuff on it

41. The CPU Z80 – 8 bit 8086 – 8 bit

42. Motherboard and its chipsetThe North bridge The North bridge The north bridge is a controller which controls the flow of data between the CPU and RAM, and to the AGP (Accelerated Graphics Port) port.

43. The South bridge The South bridge The south bridge incorporates a number of different controller functions. It looks after the transfer of data to and from the hard disk and all the other I/O devices, and passes this data into the link channel which connects to the north bridge.

44. Cache • The CPU works internally at very high clock frequencies, and normal RAM can’t keep up with these. • The solution is to insert small, intermediate stores of high-speed RAM. These buffers (cache RAM) provide a much more efficient transition between the fast CPU and the slow RAM. Cache RAM operates at higher clock frequencies than normal RAM. These are relatively more expensive. • The CPU’s cache is “intelligent”, so that it can reduce the data traffic on the bus. The cache controller constantly monitors the CPU’s work, and always tries to read in precisely the data the CPU needs. When it is successful, this is called a cache hit. When the cache does not contain the desired data, this is called a cache miss.

45. Cache and Main Memory

46. 5. The whole world is its stageI/O

47. Interacting with the rest of the worldInput, Output and External Devices Three broad categories • Human I/O • Communicating with the computer user • Video display terminals (VDTs), printers • Machine, Device I/O • Communicating with equipment • Magnetic disk and tape systems, sensors and actuators • Communication • Communicating with remote devices such as a terminal, a machine readable device, or another computer

48. Optical storage http://www.britannica.com/EBchecked/media/106454/On-optical-discs-such-as-compact-discs-and-digital-videodiscs?topicId=430490

49. Hard disk Electromagnetic Storage

50. Timing of Disk I/O Transfer Channel: The I/O communication channel between the processor and the controller onboard the disk.