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Overview

Overview. Design Requirements IceCube DAQ Reliability, QA Lessons Learned Performance. Design Requirements. Reliability / Robust Design Remotely controllable Failure must not propagate Resistant to Radio Frequency Interference Hit rate is ~1kHz Low power consumption < 5W/DOM

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Overview

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  1. Overview • Design Requirements • IceCube DAQ • Reliability, QA • Lessons Learned • Performance IceCube DAQ Design and Performance Thorsten Stezelberger

  2. Design Requirements • Reliability / Robust Design • Remotely controllable • Failure must not propagate • Resistant to Radio Frequency Interference • Hit rate is ~1kHz • Low power consumption < 5W/DOM • Surface temperatures -20°C - -70°C • At-depth temperatures -10°C - -35°C IceCube DAQ Design and Performance Thorsten Stezelberger

  3. Physics Requirements • Timing, 7ns RMS 3ns RMS • Waveform capture 300MS/s for 400ns, 40MS/s for 6.4µs • Charge Dynamic Range >200PE/15ns ~500PE/15ns • Insitu Calibration (internal and external) • Hardware Local Coincidence IceCube DAQ Design and Performance Thorsten Stezelberger

  4. IceCube • 70-80 Strings • 60 DOMs per String • IceTop Air Shower Array on top of String IceCube DAQ Design and Performance Thorsten Stezelberger

  5. DAQ System Overview Ethernet DAQ E l e c t r o n i c s IceCube DAQ Design and Performance Thorsten Stezelberger

  6. GPS Master Clock SP (String Processor) Hub DOM: “local time units” Hub: “ master time units” SP: transforms local time stamps to master time DOMs (60/string) Timedomains IceCube DAQ Design and Performance Thorsten Stezelberger

  7. DOMHub DOM Power Supplies Power Distr. Card Chassis Fans Hard Drive CPU 8 DOR Cards GPS distr. IceCube DAQ Design and Performance Thorsten Stezelberger

  8. DOM Readout Card IceCube DAQ Design and Performance Thorsten Stezelberger

  9. Main Cable • 0.9mm Twisted Quad Copper Cable • 2.5km long (continuous in ice) + Surface Cable • 2 DOMs per wire pair • Power, Timing and Communications over the same wire pair • > 50dB suppression near end cross talk • > 30 db suppression far end cross talk IceCube DAQ Design and Performance Thorsten Stezelberger

  10. Digital Optical Module Passive Base HV Supply Flasher Board Main Board Delay Board IceCube DAQ Design and Performance Thorsten Stezelberger

  11. DOM Main Board IceCube DAQ Design and Performance Thorsten Stezelberger

  12. Trigger (2) 10b FPGA ADC Pulser 1 megabaud and DOR x16 8b Delay 1 5 DAC LPF 10b SOPC ATWD 4 8 x2 +/ - 5V, 3.3V, DC - DC x0.25 10b 2.5V, 1.8V ATWD x 9 x 2.6 Configuration 10b CPU 8Mbit fADC Device MUX DP 40 MHz 32b OB - LED Ram SDRAM 16Mb (n+1) 16Mb LC SDRAM (n – 1) 20 MHz Flash Flash 16b Monitor CPLD Oscillator 4Mb 4Mb & Control Corning Frequency Ctl Flasher (was Toyocom) 8b DACs & ADCs 64 Bytes PMT Power Board 8b, 10b, 12b DOM Main Board IceCube DAQ Design and Performance Thorsten Stezelberger

  13. Trigger (2) 10b FPGA ADC Pulser 1 megabaud and DOR x16 8b Delay 1 5 DAC LPF 10b SOPC ATWD 4 8 x2 +/ - 5V, 3.3V, DC - DC x0.25 10b 2.5V, 1.8V ATWD x 9 x 2.6 Configuration 10b CPU 8Mbit fADC Device MUX DP 40 MHz 32b OB - LED Ram SDRAM 16Mb (n+1) 16Mb LC SDRAM (n – 1) 20 MHz Flash Flash 16b Monitor CPLD Oscillator 4Mb 4Mb & Control Corning Frequency Ctl Flasher (was Toyocom) 8b DACs & ADCs 64 Bytes PMT Power Board 8b, 10b, 12b DOM Main Board IceCube DAQ Design and Performance Thorsten Stezelberger

  14. Altera Excalibur • FPGA 400,000 Gates • ARM9 CPU • Bus bridges between CPU and FPGA • Dual Ported Memory between CPU and FPGA • Power consumption 0.5 – 0.7W IceCube DAQ Design and Performance Thorsten Stezelberger

  15. Trigger (2) 10b FPGA ADC Pulser 1 megabaud and DOR x16 8b Delay 1 5 DAC LPF 10b SOPC ATWD 4 8 x2 +/ - 5V, 3.3V, DC - DC x0.25 10b 2.5V, 1.8V ATWD x 9 x 2.6 Configuration 10b CPU 8Mbit fADC Device MUX DP 40 MHz 32b OB - LED Ram SDRAM 16Mb (n+1) 16Mb LC SDRAM (n – 1) 20 MHz Flash Flash 16b Monitor CPLD Oscillator 4Mb 4Mb & Control Corning Frequency Ctl Flasher (was Toyocom) 8b DACs & ADCs 64 Bytes PMT Power Board 8b, 10b, 12b DOM Main Board IceCube DAQ Design and Performance Thorsten Stezelberger

  16. ATWDAnalog Transient Waveform Digitizer • ASIC • Switched Capacitor Array • 4 Channels x 128 Samples Deep • Sampling on Launch • Sample Speed 250 - 800MSamples/s • Digitization, ~30µs/waveform • Power consumption 125mW IceCube DAQ Design and Performance Thorsten Stezelberger

  17. Trigger (2) 10b FPGA ADC Pulser 1 megabaud and DOR x16 8b Delay 1 5 DAC LPF 10b SOPC ATWD 4 8 x2 +/ - 5V, 3.3V, DC - DC x0.25 10b 2.5V, 1.8V ATWD x 9 x 2.6 Configuration 10b CPU 8Mbit fADC Device MUX DP 40 MHz 32b OB - LED Ram SDRAM 16Mb (n+1) 16Mb LC SDRAM (n – 1) 20 MHz Flash Flash 16b Monitor CPLD Oscillator 4Mb 4Mb & Control Corning Frequency Ctl Flasher (was Toyocom) 8b DACs & ADCs 64 Bytes PMT Power Board 8b, 10b, 12b DOM Main Board IceCube DAQ Design and Performance Thorsten Stezelberger

  18. Oscillator • Reference “time” of DOM • Short term stability • Screened for short term stability IceCube DAQ Design and Performance Thorsten Stezelberger

  19. Trigger (2) 10b FPGA ADC Pulser 1 megabaud and DOR x16 8b Delay 1 5 DAC LPF 10b SOPC ATWD 4 8 x2 +/ - 5V, 3.3V, DC - DC x0.25 10b 2.5V, 1.8V ATWD x 9 x 2.6 Configuration 10b CPU 8Mbit fADC Device MUX DP 40 MHz 32b OB - LED Ram SDRAM 16Mb (n+1) 16Mb LC SDRAM (n – 1) 20 MHz Flash Flash 16b Monitor CPLD Oscillator 4Mb 4Mb & Control Corning Frequency Ctl Flasher (was Toyocom) 8b DACs & ADCs 64 Bytes PMT Power Board 8b, 10b, 12b DOM Main Board IceCube DAQ Design and Performance Thorsten Stezelberger

  20. Local Coincidence • Reduce Data Rate • Rate without LC ~1KHz • Rate with LC <10Hz • Dedicated Full Duplex LC connection • Transmit and Receive go through FPGA • LC functionality can get reprogrammed IceCube DAQ Design and Performance Thorsten Stezelberger

  21. Reliability, QA Overview DOMs are not accessible after deployment • By Design • Production • Testing IceCube DAQ Design and Performance Thorsten Stezelberger

  22. Design • Qualified Manufacturer List • GIDEP (Government-Industry Data Exchange Program) • No Electrolytic Capacitors • Derate Parts • HALT (Highly Accelerated Lifetime Testing) Input • Serial number; electronic, barcode and human readable • Robust Bootstrap boot mode • Little Redundancy in the DOM (Deployed Spares) • No MTBF calculations (Temperature range) IceCube DAQ Design and Performance Thorsten Stezelberger

  23. Production • IPC610 class 3 for Board production and loading • No Microwelds in PCB • Use of Industrial Temperature Parts • Tin-Lead Parts wherever possible (NO pure tin parts) • Close work with Board manufacturer and loading house for fast feedback • Several Optical inspection Steps • Digital picture of Boards after loading • ESD Precautions IceCube DAQ Design and Performance Thorsten Stezelberger

  24. Testing • Initial room temperature Test • HASS (Highly Accelerated Stress Screening) • 48 hour Main Board burnin hot and cold • Interface test • Integrated DOM burnin 21 days at various Temp. • Test before Deployment at ~-25°C • In Summary; Testing, more Testing and even more … • All Test results are stored in Database • ESD Precautions IceCube DAQ Design and Performance Thorsten Stezelberger

  25. Lessons Learned • Test Framework (bench, integration, before deployment and after deployment) • DOMHub can run standalone • Terminal Connection to DOM • Script Language/Interpreter on DOM IceCube DAQ Design and Performance Thorsten Stezelberger

  26. Performance One String and 4 IceTop Stations are deployed • Time Calibration • Noise/Discriminator Threshold • Muon Reconstruction IceCube DAQ Design and Performance Thorsten Stezelberger

  27. for 76 DOMs Time CalibrationReciprocal Active Pulsing Verified using: • Flasher Boards • IceTop –IceCube coincidences • AMANDA – IceCube coincidences IceCube DAQ Design and Performance Thorsten Stezelberger

  28. Clock Stability Time Calibration every 3.5s IceCube DAQ Design and Performance Thorsten Stezelberger

  29. Noise/Discriminator Threshold • PMT Gain 107 • Noise in the Ice is ~800Hz • Threshold as low as ~1/8SPE IceCube DAQ Design and Performance Thorsten Stezelberger

  30. Muon Reconstruction IceCube DAQ Design and Performance Thorsten Stezelberger

  31. Summary • DAQ Design • Reliability • One IceCube string deployed • Four IceTop Stations deployed • String is working very well • All 76 DOMs function well • In Jan, Feb up to 10 more Stings deployed • Full Array deployed by 2009-10 IceCube DAQ Design and Performance Thorsten Stezelberger

  32. Thank You IceCube DAQ Design and Performance Thorsten Stezelberger

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