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antenna. channel estimation. DSP + FPGA. Sent via RF (radio waves) over the air. DSP + FPGA. 2.4 GHz ISM hardware. DSP + FPGA. detection. decoding. RF reception. DSP2. FPGA1. FPGA2. Code matched filter detector. PIC (Stage 1). PIC (Stage 2). Received bits. Detected bits.

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  1. antenna channel estimation DSP + FPGA Sent via RF (radio waves) over the air DSP + FPGA 2.4 GHz ISM hardware DSP + FPGA detection decoding RF reception DSP2 FPGA1 FPGA2 Code matched filter detector PIC (Stage 1) PIC (Stage 2) Received bits Detected bits Multiuser estimation DSP1 noise + interference Base-station Direct Reflections User 1 User 2 -2 10 -3 10 Execution time (in seconds) -4 10 BER vs Path loss in dB -5 10 -148 -140 -130 -120 -110 -102 Single DSP implementation 2 DSP implementation Target data rate - 128 Kbps/user Scheme with RF 2 DSPs + 2 FPGAs -6 RF AMP Decimation factor 10 0 5 10 15 20 25 30 35 1.00e-1 Users N RF/IF Conversion BER Decimate Filter DSP/ FPGA 1.00e-2 Baseband Simulation A/D Conversion -148 -140 -130 -120 -110 -102 AFC NCO Path loss in dB RENE: Wireless Cellular RadioSrikrishna Bhashyam, Sridhar Rajagopal, Kanu Chadha, Dinesh Rajan, Bryan Jones, Yuanbin Guo, Ahmad Khoshnevis, Frank Livingston, Charles Camp, Behnaam Aazhang, Joseph Cavallaro RENE Receiver Algorithms to Implementations Come from a Web pages antenna Channel estimator Cellular phone and - or a - Basestation (Cellular tower) Videophone calls Web page RF receiver / demodulator Detector Decoder and are… Videophone call Multimedia capabilities Algorithms (theory)… … to implementation (practice) Channel Effects Multiprocessor System at Rice Multiprocessor Simulations Asynchronous Delays Multiple Access Interference Multipath Fading Additive White Gaussian Noise DSP2 Multiuser detection • Efficient task-partitioning multiuser estimation and detection algorithms on fixed hardware • maximize performance, minimize overhead • 1.19X- 5.92X speedup with 2 DSPs. • additional processing power and internal memory • Use of FPGAs to accelerate multiuser detection • Multiple DSP-FPGA to meet real-time requirements Received bits Detected bits FPGA2 Multiuser estimation DSP1 Host DSP PC FPGA1 Prototype multiprocessor board from Sundance Inc. Two TI C67 DSPs and two Xilinx 300K gate FPGAs Inter-processor communication at 20 MBps Modeling of RF in W-CDMA with SystemView Output BW = InFs/N N: 2~64 – wideband 32~65536 - narrow Future Work Complete system evaluation on multiple DSPs and RF hardware Carrier offset and synchronization - multiple users Mobile handset - low power, fixed point DSP implementation Integrating physical layer with higher layers Task partitioning and Parallel architectures for acceleration Complete System Implementation with DSP+RF Distortion True RF modeling (IP3,P1, NF…) Multi-domain Integration ( SystemView + Matlab) Software Radio design with DDC/DDS

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