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CPUs

CPUs. Memory management Caches. The Memory System. Embedded systems and applications The memory system requirements: vary considerably Simple blocks Multiple types of memory Caches Write buffers Virtual memory. Memory management units. Memory management unit (MMU) translates addresses:

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CPUs

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  1. CPUs Memory management Caches

  2. The Memory System • Embedded systems and applications • The memory system requirements: vary considerably • Simple blocks • Multiple types of memory • Caches • Write buffers • Virtual memory

  3. Memory management units • Memory management unit (MMU) translates addresses: • Protection checks main memory logical address memory management unit physical address CPU

  4. Memory management tasks • Allows programs to move in physical memory during execution • Allows virtual memory: • memory images kept in secondary storage; • images returned to main memory on demand during execution • Page fault: request for location not resident in memory

  5. Address translation • Requires some sort of register/table to allow arbitrary mappings of logical to physical addresses • Two basic schemes: • segmented • paged • Segmentation and paging can be combined (x86)

  6. memory segment 1 page 1 page 2 segment 2 Segments and pages

  7. Segment address translation segment base address logical address + range error segment lower bound range check segment upper bound physical address

  8. Page address translation page offset page i base concatenate page offset

  9. page descriptor page descriptor flat tree Page table organizations

  10. Caching address translations • Large translation tables require main memory access • TLB: cache for address translation • Typically small

  11. ARM Memory Management Unit

  12. ARM Memory Management • System control coprocessor(CP15) • Memory • Write Buffers • Caches • Registers • Up to 16 primary registers • Physical registers in CP15 more than 16 • Register access instructions • MCR (ARM to CP15) • MRC (CP15 to ARM)

  13. Cached MMU memory system

  14. ARM Memory Management • MMU can be enabled and disabled • Memory region types: • section: 1 Mbytes block • large page: 64 Kbytes • small page: 4 Kbytes • tiny Page: 1 Kbytes • Two-level translation scheme (why?) • First-level table • Second-level table Page table size for 4-KB pages : 220 X 4 bytes = 4 MB

  15. ARM address translation Translation table base register 1st index 2nd index offset 1st level table descriptor concatenate 2nd level table descriptor physical address

  16. First-level descriptors • AP: access permission • C,B: cachability and bufferability

  17. Section descriptor and translating section references CP reg 2: 16 KB boundary 4K Entries 1 MB block (section) Max: 16KB

  18. Coarse Page table descriptor 256 entries 4 K entries Max: 16KB Max: 1KB

  19. Fine page table descriptor 1 K entries Max: 4 KB

  20. Second-level descriptor

  21. Translating large page references

  22. Access permissions • System (S) and ROM (R) in CP15 register 1

  23. TLB functions • Invalidate instruction TLB • Invalidate instruction single entry • Invalidate entire data TLB • Invalidate data single entry • TLB lockdown

  24. MPC 850 MMU

  25. MPC850 MMU • Does not support some PowerPC MMU features • 4-, 16-, 512- Kbyte, or 8-Mbyte pages • 1-KB subpages for 4-Kbyte pages • Separate instruction and data MMUs • Can be disabled separately • Supports up to 16 virtual address spaces • Supports 16 access protection groups

  26. MPC 850 MMU, cont’d • Separate 8-entry, fully-associative data translation lookaside buffer (DTLB) and instruction TLB (ITLB) • High performance and low power consumption • TLB locking, invalidation

  27. Address Translation • Translation disabled • MSR[DR], MSR[IR] • Effective address = physical address • Translation enabled • TLB • SW handles the table lookup and TLB reload with little HW assistance in the MPC 850 • MMU supports a multiple virtual address space • Address space ID (ASID)

  28. Address Translation, cont’d Not implemented in the DTLB

  29. TLB operation Current Address ID Privilege level 8?

  30. Translation Table (4 KB pages)

  31. Translation Tables (1 KB pages)

  32. Level-One descriptor

  33. Level-Two Descriptor 1KB subpage 4KB page 1KB protection 4KB page HW assist

  34. Page Size

  35. Programming Model

  36. Programming Model (cont’d)

  37. TLB operations • tlbia: translation lookaside buffer invalidate all • tlbie: translation lookaside buffer invalidate entry • Locking TLB entries

  38. Locking TLB Entries IMMU control register (MI_CTR bit 4) DMMU control register (MD_CTR bit 4)

  39. DTLB reload

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