Low-Power Dynamic Voltage Scaling System

1. Low-Power Dynamic Voltage Scaling System Taeg Sang Cho, Ravi Palakodety, Anantha Chandrakasan Massachusetts Institute of Technology

2. Outline • Introduction • Speed Detector with Adaptive Delay Scheme • Test Vector Generator • PWM Control and Buck Converter • Conclusion

3. Why Low Power?

4. How does the power numbers look? Courtesy of Wikipedia

5. Possible Optimization Space • Software • Simple Program Code (algorithm) • Efficient Compiler Technology • Hardware • Efficient Circuit Synthesis Tools • Low Power Circuit Techniques

6. Key Metric: Energy per Operation Off-current Delay per operation Switched capacitance Metric of Interest Lowering VDD will reduce the energy per operation, but will increase the delay per operation, thus incursa reliability penalty!

7. D Q D Q Dynamic Voltage Scaling (DVS) VDD = 1.2V LOGIC CLK

8. D Q D Q Dynamic Voltage Scaling (DVS) VDD = 0.3V LOGIC CLK Functionality Error!

9. Dynamic Voltage Scaling • For fixed throughput applications, minimize energy/sample in circuits. • Adjust the power supply voltage to finish critical circuit operations “just-in-time”.

10. System Block Diagram 1.2 V VDD Power Supply(DC-DC Conv) Circuit of Interest Speed Detector(Critical Path replica) System of interest in this presentation

11. Challenges of DVS • Highly efficient DC-DC converter • Low Overhead DVS control • Ensure that replica tracks real critical path in light of Threshold Voltage variations

12. Outline • Introduction • Speed Detector with Adaptive Delay Scheme • Test Vector Generator • PWM Control and Buck Converter • Conclusion

13. Delay Variation in advanced CMOS In 65nm CMOS Processes, the delay variation in circuits poses an challenge

14. Adaptive Delay Scheme Run at startup to match delay of replica and real path

15. Outline • Introduction • Speed Detector with Adaptive Delay Scheme • Test Vector Generator • PWM Control and Buck Converter • Conclusion

16. Test-Vector Generator

17. New Test-Vector Generator • We have a 50kHz clock for Accumulator!

18. Simulation Result • Power Dissipation = 546 nW • at FEXT=25MHz • Vector generator in Kuroda’s Paper • (JSSC 1998) • Power Dissipation = 2.72uW • at FEXT= 25MHz • (Simulated at 65nm process node)

19. Outline • Introduction • Speed Detector with Adaptive Delay Scheme • Test Vector Generator • PWM Control and Buck Converter • Conclusion

20. PWM Controller

21. Regulated Voltage

22. Power Dissipation in the System

23. System Specification with a Benchmark

24. Conclusion • Contribution • Implementation of Energy Efficient DVS System for Low-Power Applications : 6.4X Improvements in Power Compared with Similar Type Systems • Future work • Improvement in Loop Transient Response • Reduction in DLL Power Consumption • Continuous Adaptive-delay Element (e.g. DLL)

25. Reference [1] Variable Supply-Voltage Scheme for Low-Power High-Speed CMOS Digital Design Kuroda et al. IEEE JSSC 1998 [2] High-Efficiency Multiple-Output DC-DC Conversion for Low-Voltage Systems Dancy et al. IEEE. Trans VLSI 2000