Part I: Overview (Shaw) Part II: (Vincent) Low-Power Design Through Voltage Scaling

1. Part I: Overview (Shaw) • Part II: (Vincent) • Low-Power Design Through Voltage Scaling • Estimation and Optimization of Switching Activity • Part III: (Shaw) • Reduction of Switched Capacitance • Adiabatic logic circuit

2. Introduction

3. Motivations: • Portability • Notebook computer • Portable communication devices • Personal digital assistants (PDAs) • Green Computer • "The computer must be designed to use only non-toxic materials, to be energy efficient, and to have minimal impact on the environment in every stage of its life cycle." • Reliability

4. Methods? • Device level: Device characteristics (e.g., threshold voltage), device geometries, and interconnect properties. • Circuit level: proper choice of circuit design styles, reduction of the voltage swing, and clocking strategies. • Architecture level: smart power management of various system blocks, utilization of pipelining and parallelism, and design of bus structure. • Algorithm level: minimize the number of switching events.

5. Overview Types of Power Consumption

6. Three main components (CMOS circuit): • Dynamic (switching) power consumption • Short-circuit power consumption • Leakage power consumption

7. Switching Power Dissipation: Charge-up: one-half of the energy drawn from the power supply is dissipated as heat in conducting pMOS transistors. Charge-down: no energy is drawn from the power supply during the charge-down phase, yet the energy stored in the output capacitance during the charge-up is dissipated as heat in the conducting nMOS transistors.

8. (Periodic input with ideally zero rise- and fall-times) Assumption: output undergoes transition Reality? Node transition rate can be slower than the clock rate! Node transition factor

9. Represents the parasitic capacitance associated with each node in the circuit (including the output node) Represent the corresponding node transition factor associated with that node

10. Short-Circuit Power Dissipation:

11. Conditions: smaller output load capacitance and larger input transition times

12. Conditions: Very small capacitive load Short-circuit power dissipation Input signal rise and fall times

13. Conditions: larger output load capacitance and smaller input transition times

14. Leakage Power Dissipation: Reverse diode leakage current & subthreshold current (Reverse diode leakage current)

15. Reverse bias voltage across the junction Reverse saturation current density. The typical reverse saturation current density is Junction area

16. (subthreshold current)

17. Examples of Actual Power Dissipation:

18. Summary In addition to the three major sources of power consumption in CMOS digital integrated circuits discussed in this section, some chips may also contain circuits which consume static power. One example is the pseudo-nMOS logic circuits which utilize a pMOS transistor as the pull-up device.

19. Method #1: Reduction of Switched Capacitance System-Level Measures: • Large number of drivers and receivers sharing the same transmission medium • The parasitic capacitance of the long bus line.

20. Circuit-Level Measures: The capacitance is a function of the number of transistors that are required to implement a given function Pass-gate logic CMOS circuit XOR logic

21. Mask-Level Measures: The parasitic gate and diffusion capacitances of MOS transistors in the circuit typically constitute a significant amount of the total capacitance in a combinational logic circuit. Hence, a simple mask-level measure to reduce power dissipation is keeping the transistors (especially the drain and source regions) at minimum dimensions whenever possible and feasible.

22. minimum dimensions?? Trade-off: Dynamic performance of the circuit Power dissipation

23. Method #2: Adiabatic Switching • Adiabatic switching is also called energy-recovery • “Adiabatic” describe thermodynamic process that exchanges no heat with the environment • Keep potential drop switching device small • Allow the recycling of energy to reduce the total energy drawn from the power supply

24. CMOS Switching Transition of the output: How much is the stored energy? No charge is drawn from the power supply and the the energy stored in the load capacitance is dissipated in the nMOS network Transition of the output:

25. Adiabatic Switching:

26. Less dissipation only if: • Current is constant and • Least power dissipation <- slowest transition • Energy dissipation is not only depend on the capacitance and swing voltage, but also proportional to the output resistance.

27. An example of Adiabatic Switching: Adiabatic amplifier circuit which transfers the complementary input signals to its complementary outputs through CMOS transmission gates

28. Adiabatic Logic Gates: The general circuit topology of a conventional CMOS logic gate The topology of an adiabatic logic gate implementing the same function

29. Circuit diagram of an adiabatic CMOS

30. Stepwise Charging Circuits: A CMOS inverter circuit with a stepwise-increasing supply voltage

31. Equivalent circuit, and the input and output voltage waveforms of the CMOS inverter circuit

32. Analysis: Solving this differential equation with the initial condition

33. Stepwise driver circuit for capacitive loads. The load capacitance is successively connected to constant voltage sources Vi through an array of switch devices

34. Tradeoff!! Reduction of energy dissipation Expense of switching time

35. Adiabatic families: • Partially Adiabatic Logic • 2N2P / 2N-2N2P • CAL (Clocked CMOS Adiabatic Logic) • TSEL (True Single Phase Adiabatic) • SCAL (Source-coupled Adiabatic Logic) • Fully Adiabatic Logic • PAL (Pass-transistor Adiabatic Logic) • Split-level Charge Recovery Logic (SCRL)

36. Periodic ramp-like clocked power supply 2N2P Inverter vs CMOS Inverter Vdd PC o o out /out /in in out in o Q=CV I=Q/T; T CMOS Inverter 2N2P Inverter

40. 2N-2N2P Inverter The primary advantage of 2N-2N2P over 2N2P is that the addition of the cross-coupled Nfets results in non-floating data valid over 100% of the HOLD phase.

41. Analysis: • Reset Phase: • The high output will ride down only to Vt,p, rather than GND. • Wait Phase: • Floating at 0 and Vt,p • Evaluation Phase: • If State has not changed • If changed(nonadiabatic power consumption is )

42. Characteristics of 2N2P / 2N-2N2P • Cascades require four-phase clocks • Non-adiabatic occurs at brief interval in the beginning of the evaluation phase • Non-adiabatic dissipation proportional to • Both inverting and non-inverting output available

43. CAL Inverter Cascades require single-phase clock and two auxiliary square-wave clocks PCK o o F1 F1 CX CX F0 F0

45. Simulated switching energy-vs-frequency curves