1 / 11

DAQ Selection Discussion

DAQ Selection Discussion. DAQ Subgroup Phone Conference Christopher Crawford 2013-01-11. Reminder – from April DOE review Event / Data rate < 5000/s decay rate in active volume; 600/s protons in upper detector

christine-burt
Download Presentation

DAQ Selection Discussion

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. DAQ Selection Discussion DAQ Subgroup Phone Conference Christopher Crawford 2013-01-11

  2. Reminder – from April DOE review • Event / Data rate • < 5000/s decay rate in active volume; 600/s protons in upper detector • Coincident electron in adjacent pixel (7/127), either top or bottom detector • Accidentals from decay products <1% for 40 us coincidence window • PIXIE-16 waveform digitizer: 100 MHz sample rate, 12 bit ADC • 14 pixels * 1 us * 100 MS/s * 12 bit * 5000 /s = 11 MB/s; 12 TB / 2 weeks • Trigger scheme • Trigger levels: 1) DIGITIZER threshold, 2) FPGA readout, 3) CPU storage • Trigger separately on protons / electrons, form coincidences in software • Energy sum trigger for adjacent pixels – detection of lower-threshold events • Read out 6 neighboring pixels around trigger • Local trigger decisions based on hit information from other modules: digitizer FPGA main FGPA readout hits fiber optics PXI bus trigger lines rear I/O module

  3. Trigger options Levels: • Overthreshold in single pixel • Coordinated readout in FPGA • Validation in CPU before write to disk Data Rates: 14 pixels x 12 bits x 100MS/s Trigger Options: • Independent e, p: 13 MB/s filter coincidence in CPU • Proton trigger: 51 MB/s search for e in CPU (no advantage?) • Electron trigger: 480 MB/s search for p in CPU (no advantage?)

  4. Trigger options Multipixel clustering: • Coordinated readout: easier/important for offline energy construction • Energy sum trigger: harder/relevant? low energy protons in 1 pixel • Coincidence of multiple hits in L2 trigger logic – doesn’t require trap. filter • Query total energy from neighbors of single hit – higher efficiency • Low threshold trigger: average signal before discrimination Multiple thresholds Single threshold

  5. XIA system • $280k including spare digitizer module; price break on RTM • Good support: FPGA & optical Rear Transition Module development • 250 MHz, 14 bit fADC; excellent energy reconstruction algorithms

  6. XIA custom firmware • Overlapping pileup trigger • Record back-to-back events • Multichannel readout • Each pixel broadcasts threshold and pixel # • Each module decides which pixels to readout according to lookup table • Energy sum (cluster) trigger • 3 separate thresholds (2 bits) broadcast with pixel # • Lookup table extended for all combinations of pixel/threshold • Alternative: single-threshold cluster based on full energy information a) hit broadcasts energy b) neighbors broadcast energy c) discriminate on sum • Trigger distribution bus • 38 global + 52 half crate + 21 nearest neighbor lines • Note: enough lines to broadcast 4 pixel# + 8 energy bits per module (more if we only do cluster trigger for pixels in fiducial volume)could even discriminate on sum of 8-bit energies

  7. NI system • $300k, (discounted from $850k) • All communications on fiber PCIe bus - FAST • Different digitizer architecture: • 16 bit, 120 MHz • data is continuously written to single 512 MB ring buffer • CPU can request any ranges of data within the last 0.5 s • Convenience of programming: • Level 1 trigger is implemented in FPGA, written in LabVIEWwe could include trapezoid filters to calculate the energy sum • Level 2/3 triggers implemented in CPU easy to implement powerful global triggersfast communication via DMA over PCIe bus • Could implement energy sum trigger by adding up total energy • Low-threshold pixel prompts reading energy of all neighbors • Level 2 trigger on energy sum • Lossless for a threshold of E0/n assuming n-pixel events

  8. NI architecture

  9. Jlab system • Based on custom hardware for 12 GeV upgrade: $128 total • 2*$9k  VXS crate (VME 2eSST + serial fabric on J0 with a double-star topology to two switchboards) (page 5) • 2*$6k  single-board computer (SBC) which runs entire DAQ software, writes out to RAID • 2*$5k  crate trigger processor (CTP) with VirtexV FX70T, 5 Gbps to fADCs, 8 Gbps fiber to other crate (pate 21) • 2*8*$5k  16-ch 250 MHz, 12 bit fADC digitizers with 2eSST readout, but only 4x 4 us ring buffer (page 23) • High-speed connection (50 bits/cycle) from each module to CTP • Could implement powerful global trigger in FPGA • We have to develop entire firmware and software ourselves • Would cost $100k for engineer for 1 year, uncertain schedule

  10. CAEN system • $260k not including optical links between detectors • External FPGAs connected to modules by ribbon cable • We would have to develop global trigger logic, and design optical link between crates

More Related