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40G Signal Tap (sniffer) – Yearly Project Part 1 – 10G Signal Tap First presentation

40G Signal Tap (sniffer) – Yearly Project Part 1 – 10G Signal Tap First presentation. Intel: Lan Access Division Technion: High Speed Digital Systems Lab. By: Leonid Yuhananov & Asaad Malshy Supervised by: Dr. David Bar-On. 10G/40G Tap agenda. Goal Challenges Proposed solution:

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40G Signal Tap (sniffer) – Yearly Project Part 1 – 10G Signal Tap First presentation

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  1. 40G Signal Tap (sniffer) – Yearly Project Part 1 – 10G Signal TapFirst presentation Intel: Lan Access Division Technion: High Speed Digital Systems Lab By: Leonid Yuhananov& Asaad Malshy Supervised by: Dr. David Bar-On

  2. 10G/40G Tap agenda • Goal • Challenges • Proposed solution: • Block diagram. • description. • Plan • Gantt chart. • Deliverables: • Semester 10G. • Yearly 40G.

  3. Goal “Tracing 40Gbit Ethernet on a logic analyzer” We want to tap onto 40G traffic and present it in a useful way. • Tap: Listen to the Link. • Sniff the data transmitting on the line. • Present: View data on Logic analyzer. • Parse the data into Ethernet II frames. • Useful: Easy to read and good for debug. • Only the frames we are interested in will be presented.

  4. Deliverables • 10G Signal tap after first semester. • Ability to tap and present 10G traffic. • 40G Signal tap at the end of the year. • Ability to tap and present 40G traffic. • Configure parameters of trigger. • GUI.

  5. 10G/40G Tap agenda • Goal • Challenges • Proposed solution: • Block diagram. • description. • Plan • Gantt chart. • Deliverables: • Semester 10G. • Yearly 40G.

  6. Challenges • Logic Analyzer is not fast enough for direct tap. • Use De-Serializer based on FPGA • How can we process 10G traffic using our 600MHZ FPGA? • Use special FPGAs with 10G ser-des built-in • Word alignment becomes an issue that requires a solution. • Comma detection block. • Creating a trigger for the logic analyzer. • Trigger will need to be configurable. • Syncing the trigger signal with the data. • Working with an unfamiliar environment (Altera). • Small introduction exercise. • Time management: • Using Gantt chart.

  7. 10G/40G Tap agenda • Goal • Challenges • Proposedsolution: • Block diagram. • description. • Plan • Gantt chart. • Deliverables: • Semester 10G. • Yearly 40G.

  8. Proposed Solution Duplicates the optical line 1->2 10G NIC 10G NIC Optical link Optical -> Electrical • Use a Altera ready made Ser-des board. • Using the MegaWizard™ to configure the hardware. • Quartus II will be our main development environment.

  9. Preliminary Block Diagram • Deserializer : HW blocks of Stratix • PCS: FPGA RTL code for synchronization and interpretation. • Processing: Trigger and filter data. • Data rate multipliers: serialazier to logic

  10. 10G/40G Tap agenda • Goal • Deliverables: • Semester 10G. • Yearly 40G. • Challenges • Proposed solution: • Block diagram. • description. • Plan • Gantt chart.

  11. Gantt

  12. Next • Creating a basic data path using Altera. • Designing the micro-architecture of our final solution. • High level RTL block diagram. • Design of each block on logical level.

  13. Thank you all Stay tapped for more 

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