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CMS Tracker FED Back End FPGA

CMS Tracker FED Back End FPGA. Clock40. Frame_Sync_out0. Frame_Sync_In0. Reset. Readout_Sync_out0. TTCrx. Readout_Sync_In0. Monitor_out0. 16. VME Internal. FE0. Monitor_In0. ~80. Config_In0. TTS. Config_out0. Data_stream0. 8 Clock40. Frame_Sync_out7. SLINK64. 64.

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CMS Tracker FED Back End FPGA

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  1. CMS Tracker FED Back End FPGA Clock40 Frame_Sync_out0 Frame_Sync_In0 Reset Readout_Sync_out0 TTCrx Readout_Sync_In0 Monitor_out0 16 VME Internal FE0 Monitor_In0 ~80 Config_In0 TTS Config_out0 Data_stream0 8 Clock40 Frame_Sync_out7 SLINK64 64 Frame_Sync_In7 SLINK Readout_Sync_out7 16 Readout_Sync_In7 ADDR/CNTRL FE7 Monitor_Sync_out7 DATA IN 18 QDR SSRAM x2 Monitor_Sync_In7 18 DATA OUT Data_stream7 Bank DCI Resistors Full flags 3 2 Temp Flags Configuration Temp Sense Bank Voltages LM82 BSCAN Core Voltage

  2. CMS Tracker FED Back End FPGA x2 BSCAN 1 Clock40 x4 DCM x1 diagnostics Circular Buffers 1 ‘VME’ 8 Control Header 64 64 Data SLINK Reset 1 80 MHz APV hdrs x8 Frame_Syncs FIFO x8 DECODE CONTROL & MONITOR Readout_Syncs Lengths x8 18 Data Out Monitor_Syncs FIFO 320 MHz 2 FF/PF Flags QDR SSRAM x4 burst Bx,Ex Lengths FIFO 40 Mhz R/W Address Generator 9 TTC Rx 20 Address Em Hdr TTS 80 MHz FIFO 100 Khz 8 Data_stream0 64 18 Data In 80 Mhz 8 320 MHz Data_stream7 80 MHz

  3. CMS Tracker FED - Back End FPGA Floorplan Die Package VME FE_FPGA_Inputs SLINK QDR Same frame 456 & 676 ? XC2V1000FG456 - 324 I/O Clocks XC2V1500FG676 - 396 I/O XC2V2000FG676 - 456 I/O XC2V3000FG676 - 484 I/O

  4. CMS Tracker FED Back End FPGA #FFFFF Event N+1 Event N+1 Event N+1 Write Ptr 7 FE 7 Write Ptr 7 Write Ptr 7 Write Ptr 2 Event N Write Ptr 2 Write Ptr 2 Write Ptr 1 FE 1 Write Ptr 0 Write Ptr 1 Write Ptr 1 FE 0 Header Ptr Write Ptr 0 Write Ptr 0 Header Ptr Header Ptr Read Ptr Event N-1 Event N-1 Event N-1 Read Ptr Read Ptr #00000 T0 T1 T2

  5. CMS Tracker FED Back End FPGA Channel Link x1 1 Clock40 DCM x2 3 x4 Control 3 16 SLINK ‘VME’ In 16 Out Header 8 DDR 64 8 640 MHz LVDS Control Data 8x Reset 1 CSM x8 BR DPMs Frame_Syncs x8 APV Hdr Readout_Syncs DECODE CONTROL & MONITOR x8 BR FIFO Load_monitor 18 Lengths x8 Data Out BR FIFO Spare 320 MHz Bx/Ex 2 FF/PF Flags BR FIFO QDR SSRAM x2/x4 burst 8 Lengths Em Hdr 40 Mhz R/W Address Generator BR FIFO 9 8 Pointers TTC Rx 20 Address TTS 80/160 MHz Control 4 Data_stream 0 64 18 Data In DDR 4 320 MHz 80 MHz Data_stream 7 160 MHz

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