Design of State Machines: Mealy and Moore Systems

1. Lecture 14State Machines II CSCE 211 Digital Design • Topics • State Machine Design • Resolution with Text • Design with D flip-flops • Design with JK • Readings: Chapter 7 November 11, 2015

2. Overview • Last Time • State machine construction • HW $.50 coke machine with no change • New • State machine construction again (text notation) • Next Time: • Test 2 : Nov 16th next Monday

3. P = (S + Q)´ Q = (R + P)´

7. Continuing Examples (CE) CE7.A Mealy system with one input x and one output z such that z = 1 at a clock time iff x is currently 1 and was also 1 at the previous two clock times. CE8. A Moore system with one input x and one output z, the output of which is 1 iff three consecutive 0 inputs occurred more recently than three consecutive 1 inputs. CE9.A system with no inputs and three outputs, that represent a number from 0 to 7, such that the output cycles through the sequence 0 3 2 4 1 5 7 and repeat on consecutive clock inputs. CE10.A system with two inputs, x1and x2, and three outputs, z1, z2, and z3, that represent a number from 0 to 7, such that the output counts up if x1= 0 and down if x1 = 1, and recycles if x2 = 0 and saturates if x2 = 1. Thus, the following output sequences might be seen x1 = 0, x2 = 0: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 … x1 = 0, x2 = 1: 0 1 2 3 4 5 6 7 7 7 7 7 7 7 7 7 … x1 = 1, x2 = 0: 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 … x1 = 1, x2 = 1: 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 … (Of course, x1, and x2 may change at some point so that the output would switch from one sequence to another.)

8. Step 1: From a word description, determine what needs to be stored in memory, that is, what are the possible states. Step 2: If necessary, code the inputs and outputs in binary. Step 3: Derive a state table or state diagram to describe the behavior of the system. Step 4: Use state reduction techniques (see Chapter 7) to find a state table that produces the same input/output behavior, but has fewer states. Step 5: Choose a state assignment, that is, code the states in binary. Step 6: Choose a flip flop type and derive the flip flop input maps or tables. Step 7: Produce the logic equation and draw a block diagram (as in the case of combinational systems).

11. D1 = x q2 + x q1 D2 = x q´2 + x q1

14. J1 = xq2 K1 = x´z =q1q2 J2 = x K2 = x´ + q´1

15. S1 = xq2R1 = x´z =q1q2 S2 = xq´2R2 = x´ + q´1q2

17. T1 = x´q1 + xq´1q2 T2 = x´q2 + xq´2 + xq´1q2 z =q1q2

23. z =x´ + q1q2 D1 = x´ + q´1 + q´2 D2 = xq´2 + xq´2 J1= 1 K1 = xq2 J2 = x´K2 = x´

25. DA = xAC´ + xBC DB = x´A + x´B + x´C DC = x´A + x´B + x´C´ + AC´ z = A + BC JD =KD =CBA JC =KC =BA JB =KB =A JA =KA = 1

26. JA =KA = 1 JB =KB =x´A +xA´ JC =KC =x´BA +xB´A´

27. 0, 3, 2, 4, 1, 5, 7, and repeat

28. D1 = q´2q3 + q2q´3 D2 = q´1q´2q´3 + q´1q2q3 + q1q´2q3 D3 = q´2

29. q1 = 1, q2 = 1, and q3 = 0 D1 = q´2q3 + q2q´3 = 00 + 11 = 1 D2 = q´1q´2q´3 + q´1q2q3 + q1q´2q3 = 001 + 011 + 100 = 0 D3 = q´2 = 0

30. CE6. A system with one input x and one output z such that z = 1 iff x has been 1 for at least three consecutive clock times.

31. A none, that is, the last input was 0 B one C two D three or more

32. CE7. A system with one input x and one output z such that z = 1 at a clock time iff x is currently 1 and was also 1 at the previous two clock times. CE7#. A Mealy system with one input x and one output z such that z = 1 iff x has been 1 for three consecutive clock times.

34. A none, that is, the last input was 0 B one C two or more

36. Design a Mealy system with one input x and one output z such that z = 1 iff x has been 1 for exactly three consecutive clock times. A sample input/output trace for such a system is x 0 1 1 1 1 1 1 1 0 1 1 0 1 1 1 0 1 z 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 ↑ ↑ A none, that is, the last input was 0 B one 1 in a row C two 1’s in a row D three 1’s in a row E too many (more than 3) 1’s in a row

37. Design a Moore system with one input, x, and one output z such that z = 1 iff x has been 1 for exactly three consecutive clock times. x 0 1 1 1 1 1 1 1 0 1 1 0 1 1 1 0 1 z 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0

38. CE8. Design a Moore system whose output is 1 iff three consecutive 0 inputs occurred more recently than three consecutive 1 inputs. A sample input/output trace for such a system is x 1 1 1 0 0 1 0 1 1 1 0 0 1 0 0 0 0 1 1 1 1 0 1 z ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0

39. CE11. Design a Moore model bus controller that receives requests on separate lines, R0 to R3, from four devices desiring to use the bus. It has four outputs, G0 to G3, only one of which is 1, indicating which device is granted control of the bus for that clock period. The low number device has the highest priority, if more than one device requests the bus at the same time. We look at both interrupting controllers (where a high priority device can preempt the bus) and one where a device keeps control of the bus once it gets it until it no longer needs it. The bus controller has five states: A: idle, no device is using the bus B: device 0 is using the bus C: device 1 is using the bus D: device 2 is using the bus E: device 3 is using the bus

43. Read Only Memory Functionality

44. 3-Input 4-Output ROM D0 OR A0 OR D1 A0 3x8 decoder A1 OR D2 A2 OR D3

45. Construction of a 2 x n ROM • Zap some connections during construction • Denoted “x” d0 d1 A0 2x4 decoder d2 A1 d3 … Y0 Y1 Y2 Yn-1

46. 2x4 Decoder with Output-Polarity Control • Figure 9-2

47. Implementing Arbitrary Boolean functions with ROMs

48. Multipliers in ROM • Figure 9-4

49. Logic Diagram of 8x4 diode ROM • x 74LS138 =1-OF-8 DECODER/ DEMULTIPLEXER

50. Two-Dimensional Decoding