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4-bit Full-Adder With Ripple Carry

4-bit Full-Adder With Ripple Carry. Adrian Corona Tuessia Ly Ali N. Warriach Advisor: Dave Parent Dec. 6, 2004. Agenda. Abstract Introduction Why Simple Theory Back Ground information (Lit Review) Summary of Results Project (Experimental) Details Results Cost Analysis Conclusions.

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4-bit Full-Adder With Ripple Carry

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  1. 4-bit Full-Adder With Ripple Carry Adrian Corona Tuessia Ly Ali N. Warriach Advisor: Dave Parent Dec. 6, 2004

  2. Agenda • Abstract • Introduction • Why • Simple Theory • Back Ground information (Lit Review) • Summary of Results • Project (Experimental) Details • Results • Cost Analysis • Conclusions

  3. Abstract • We attempted to design a 4-bit Full Adder with Ripple carry that operated at 200 MHz and uses less than 23W/cm2 of Power and occupied an area of 295x68mm2

  4. Introduction • Ripple Carry Full Adders are foundation for other logics. • It serves as a basic tool for Carry Look Ahead adders which are used for MSI adders and ALUs.

  5. Project Details • Hand Calculations • Cell based technique - Built and created each layout of 1-bit separately and tested LVS. • Final Schematic • Final Layout • Final Simulation

  6. Longest Path Calculations

  7. Schematic

  8. Layout

  9. Layout w/o FF

  10. Verification

  11. Simulations

  12. Cost Analysis • Time spent on each phase of the project • Verifying logic = 3 hours • Verifying timing = 12 hours • Layout = 20 hours • Post extracted timing = 4 hours

  13. Lessons Learned • Get extremely familiar with the Cadence tool. • Plan ahead and stay on schedule. • Get professor’s advice more often.

  14. Summary • Our design of 4-bit Full Adder with Ripple Carry is a building block for Carry Look Ahead adder which can further be used for MSI adders and ALUs. • We were successful in proving that our design works without the Flip Flops. • In future we think its better to work with the Carry Look Ahead adder instead.

  15. Acknowledgements • Thanks to our significant others for bearing our time away from home. • Thanks to Cadence Design Systems for the VLSI lab • Thanks to Synopsys for Software donation • Thanks to Dr. Parent for his patience and valuable lessons.

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